Amplificadores a Um e Dois Transistores
Transcript of Amplificadores a Um e Dois Transistores
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• Seleção do modelo para análise aproximada do circuito analógico
– Selecionar o modelo mais simplificado possível e que ainda continue descrevendo o comportamento do circuito dentro de uma faixa de erro tolerável.
– Fazer uma análise teórica preliminar com este modelo afim de obter uma compreensão intuitiva dos fatores que afetam o comportamento do circuito de modo que um procedimento interativo de projeto leve a um desempenho melhor do circuito.
– Qual modelo utilizar ? - Projetar, projetar, projetar... Não existe uma regra.
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ICTB
E
C
B’
E’
C’
rb’
rc’
re’
CDC
CDE
CJC
CJE
CCS ouCSUB
EM2 - Modelo Completo - NPN
IEC/βR=IS/βR(eqVB’C’/kT
-1)
ICC/βF =IS/βF(eqVB’E’/kT
-1)
ICC - IEC
=
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EM2 – Modelo de pequenos sinais linearizado
rπ gmFVF-gmRVR
+_
CCSUB
BB’
rb’
VF
E
rc’
re’
Cπ
Cµ
rµ
+ _VR
E’
C’
Modelo ππππ-híbrido
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• Estágios amplificadores básicos com BJT (pequenos sinais)
= +
Transistores operando na região ativa.
iC = IC + ic
iE = IE + ie
iB = IB + ib
Análise DC Análise AC
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• Amplificadores de duas portas– Parâmetros de quadripolo :
2221212
2121111
vhihi
vhihv
+=+=
2221212
2121111
vyvyi
vyvyi
+=+=
2221212
2121111
izizv
izizv
+=+=
ParâmetrosHíbridos
Parâmetrosde Admitância
Parâmetrosde Impedância
Quadripolo
i2
i2
i1
i1
+
-
+
-v1 v2
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• Parâmetros de admitância de quadripolo :
2221212
2121111
vyvyi
vyvyi
+=+=
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
111
2 ==
vvi
y
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2 Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
221
2 ==
vvi
y
02
112
1 =
=v
vi
y
02
222
1==
vvi
y
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• Parâmetros de impedância de quadripolo :
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
111
2 =
=i
iv
z
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2 Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
221
2 =
=i
iv
z
02
112
1 =
=i
iv
z
02
222
1=
=i
iv
z
2221212
2121111
izizv
izizv
+=+=
i1
i1
+
-
v1
i2
i2
+
-
v2
z11 z22
z12.v2z21.v1
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• Parâmetros híbridos de quadripolo :
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
111
2 =
=v
iv
h
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2 Quadripolo
i2
i2
i1
i1
+-
+-
v1 v2
01
221
2 =
=v
ii
h
01
212
1 =
=i
vv
h
02
222
1=
=i
vi
h
i1
i1
+
-
v1
i2
i2
+
-
v2
h11
h22h12.v2
h21.v1
2221212
2121111
vhihi
vhihv
+=+=
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• Amplificador é dito bilateral se x12≠0 e x21≠0 e unilateralse x12=0
– v1 e i1 não dependem das conexões nas portas de saída ( i2 , v2 )
– ocorre em muitos casos práticos, principalmente em baixa frequência
111 yZi =
,
221 yZo =
,
21yGm =
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• Três configurações básicas:– Emissor comum– Coletor comum– Base comum
• Estágios amplificadores básicos com BJT (pequenos sinais)
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• Emissor Comum (CE)
Modelo equivalente π-hibrido•baixa frequência•rb << rπ. •rµ negligenciado.
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Onde:
mi
ii g
riv
R 0βπ ===
mvi
m gii
G ===0
0
0
000
00 || rR
iv
R Cvi
===
Ganho de tensão de circuito aberto ( sem carga na saída):
( )Cm
iiv Rrg
vv
a ||0
0
0
0
−===
se RC émuito grande η
10 −=−==−=∞→
T
A
C
A
T
CmRv V
VIV
VI
rgaC
Ganho de corrente ai :
00
0
0
βπ =====
rg
Rv
Gii
a m
i
i
m
vii
Configuração emissor comum: •ganho de tensão •ganho de corrente•.etc.
→valor típico5000 p/ NPN.
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• Base Comum (CB)
πrg
r
m
e 11
+=
Preferencialmente se utiliza o modelo T.
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• Circuito equivalente para análise,
• Na análise será considerado: rµ→∞(unilateral), rb = 0, desprezou o efeito de rµ e considerou operação em baixa frequência.
Assim,
mm gG = ei rR = Co RR =
Cmomv RGRGa == 00
01
αβ
β=
+=== emimi rgRGa
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• Considerando rb>0 :
• São dois os principais motivos para utilizar a configuração base comum:– não realimentação em alta frequência– resistência de saída muito maior quando RC →∞. Bom
para fonte de corrente: corrente da fonte de corrente é praticamente independente da tensão sobre ela
πrr
gG
b
mm
+=
1
���
����
�+=��
�
����
�+
+=
ππ
αβ r
rgr
rrR b
m
bei 11
10
0
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• Configuração base comum com ro finito– O circuito se torna bilateral: Ri depende de RL
– Ro depende passa a ter influência de ro
meideali g
rR 0)(
α== CRR =
Gm não depende da relação entre ro e RC (saída curto-circuitada) e sem
o Gr
1>>
mm gG ≅
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• Resistência de entrada em base comum
• Se ,
• E também ,
( ) ( )[ ]oLCm
LCo
e
LCoLCm
LCo
i
ti
rRRg
RRr
rRRr
RRG
RRriv
R1||1
||||
||1
||
00
+++
+=
++−
+==
ββ
( ) LCo RRr ||.10 >>+β
01
||
αom
LCoi rg
RRrR
+
+≅
0. α>>om rg
( ) ( )om
LCe
om
LC
mi rg
RRr
rgRR
gR
|||| 000 ααα+=+≅
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• Resistência de saída em base comum
�����
�
�
�
+
���
����
�++
=
�����
�
�
�
−+
���
����
�++
=���
����
�=
π
α
rR
rgRr
Rgm
rR
rrRr
Riv
RRS
omSo
eS
oeSo
t
to
1
1
||11
111
|||| 0
Ro
RS << rπ
gmro >>α0
gmRS >>α0
RS << rπRS →∞RS = 0
orR ||���
�
����
����
� ++
0
1||
αom
Sorg
RrR���
�
����
����
� +πα
rrg
R om
0
1|| ��
�
����
�S
om Rrg
R0
||α
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• Coletor Comum (CC) ou Seguidor de Emissor
• Outra configuração bilateral
• Quando :LoS RreRr >>>>>> 1, 0βπ
( )( )oL
Ss
o
rRrRv
v
||11
1
0 ++
+=
βπ
Lm
Lm
s
oRg
Rgvv
+≅
1
→ relação menor que 1
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( )( )oLt
ti rRr
iv
R ||10 ++== βπ
oS
t
to r
Rriv
R ||10���
����
�
++
==βπ
Se :1
11
00 +
+>>>>β
β S
mo
Rg
re
11
0 ++≅
βS
mo
Rg
R
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• Configuração emissor comum com degradação de emissor ( emitter degeneration)
– Introdução de uma resistência no emissor ( parasita ou intencional) :
• redução da transcondutância• aumento da resistência de entrada/saída do amplificador.
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• Resistência de entrada:
• Se ,
• Transcondutância
• Na prática
( )����
�
�
����
�
�
+++
+++==
ECo
Co
Eb
ii RRr
Rr
Rriv
R1
1 00
ββπ
EoCo RreRr >>>>( ) E
b
ii Rr
iv
R 10 ++== βπ
�����
�
�
�
���
����
�+++
−==
omEm
o
E
i
om
rgRg
rR
gmvi
G11
11
1
0
0
β
β
1.,10 >>>>>> omEo rgeRrβ
Emi
om Rg
gmvi
G+
=≅1
![Page 25: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/25.jpg)
• Resistência de saída (para RL muito grande de forma que pode ser desconsiderado):
• considerando o segundo termo muito maior:( ) ( )[ ]EmoEo RrgrRrR ||1|| ππ ++=
����
�
�
�
++≅
01
1
βEm
Emoo Rg
RgrR
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• Para
• caso contrário
• Se RC não é desprezível, o novo valor de Ro será o resultado do paralelo de RC com o valor de Ro calculado desprezando-se RC.
0β<<Em Rg
[ ]Emoo RgrR +≅ 1 → resistência de saída aumentada
0β>>EmRg
[ ]01 β+≅ oo rR
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• Estágios amplificadores com vários transistores
- Vários estágios amplificadores acoplados buscando: ganho de tensão, corrente, e/ou transformação de impedância da entrada para saída
- Configurações básicas de cascateamento mais utilizadas:
• Coletor comum (CC) Emissor comum(EC)• Coletor comum (CC) Coletor comum(CC)• Darlington
• Cascode → aumenta a resistência de saída e reduz as capacitâncias parasitas de realimentação.
Melhorar o desempenho de ganho de corrente e impedância de entrada de um transistor bipolar básico.
![Page 28: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/28.jpg)
• Configuração CC-CE, CC-CC
Q1 - aumentar a resistência de entrada e o ganho de corrente
![Page 29: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/29.jpg)
• Quando, IBIAS = 0 tem-se IB2=IE1 , o que resulta:
• Paro o circuito equivalente tem-se:
( ) 201 1 πππ β rrr c ++=
( ) ���
����
�
++
=
20
1
2
11
π
πβ r
r
gg mc
m
2oco rr =
22mc
m
gg =
e
( )100 +== βββ cb
ccc
ii
![Page 30: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/30.jpg)
• Configuração Darlington
•Na configuração emissor comum:•diminui a resistência de saída devido a realimentação através de ro•aumenta a capacitância de entrada devido a conexão coletor-base de Q1. Melhor usar a configuração CC-CE.
![Page 31: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/31.jpg)
• Configuração cascode (CE-CB)
1πrRi = 1mm gG ≅����
�
�
����
�
�
++=
0
12
122 .
1
.1
βom
omoo rg
rgrR
Se ,1. 0012 >>>> ββ erg om
,
02βoo rR =
E o ganho de tensão com a saída em aberto é:ηββ 0
021 −=−≅−= omomv rgRGA
![Page 32: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/32.jpg)
• Par diferencial– Configuração mais utilizada em circuitos
integrados por dois motivos:• O cascateamento de pares diferenciais pode ser feito
sem necessidade de acoplamento capacitivo• Alta rejeição a sinais e ruídos de modo comum.
![Page 33: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/33.jpg)
• Característica de transferência ( ro, REE→∞ e rb =0 )
Assumindo que os transistores operam na região ativa (resistores RC suficientemente pequeno) Vi1 ≤ VCC e Vi2 ≤ VCC. E também Vbe1 >> VT e Vbe2 >> VT o modelo Ebers-Moll:
Assumindo transistores indênticos IS1= IS2
02211 =−+− ibebei VVVV
���
����
�=��
�
����
�=
2
22
1
11 lnln
S
CTbe
S
CTbe I
IVVe
II
VV
���
����
�=��
�
����
� −=T
id
T
ii
C
C
VV
VVV
II
expexp 21
2
1
![Page 34: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/34.jpg)
CcCCo
CcCCo
RIVV
RIVV
22
11
−=−=
���
����
�−=−=
T
idEEFooo V
vIVVV
2tanh211 α
( )F
ccEEee
IIIII
α21
21
+==+−
���
����
�+
⋅=
���
����
�−+
⋅=
T
id
EEFc
T
id
EEFc
VV
II
VV
II
exp1
exp1
2
1
α
αe αF1= αF2= αF
Para saída
![Page 35: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/35.jpg)
• Característica de transferência ( ro, REE→∞ e rb =0 ):
���
����
� −=−=
T
idCEEFoood V
VRIVVV
2tanh21 α
![Page 36: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/36.jpg)
• Com emissor degenerado:
![Page 37: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/37.jpg)
• Análise de pequenos sinais de amplificadores diferencias
���
+=+=
→���
==
2221212
2121111sinaispequenospara
212
211
),(
),(
iio
iio
iio
iio
vAvAv
vAvAv
VVgV
VVfV
01
222
01
221
02
112
01
111
12
12
==
==
==
==
ii
ii
vi
o
vi
o
vi
o
vi
o
vv
Avv
A
vv
Avv
A
Onde,
![Page 38: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/38.jpg)
• Como o que interessa geralmente é relação diferencial na entrada/saída, a descrição anterior não é muito intuitivo. Assim , são definidas novas variáveis associadas ao comportamento diferencial e de modo comum
���
���
�
−=
+= →←
��
��
�
+=
−=
2
2
2 2
1
21
21
idici
idicirelação
iiic
iiid
vvv
vvv
vvv
vvv
De forma idêntica para saída,
���
���
�
−=
+= →←
��
��
�
+=
−=
2
2
2 2
1
21
21
odoco
odocorelação
oooc
oood
vvv
vvv
vvv
vvv
![Page 39: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/39.jpg)
:
Substituindo os termos 2121 e,, ooii vvvv
( )
icidoc
icidod
vAAAA
vAAAA
v
vAAAAvAAAA
v
��
���
� ++++�
�
���
� −+−=
−−++��
���
� +−−=
24
2
2221121122211211
2221121122211211
![Page 40: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/40.jpg)
• Portanto:
iccmidcmdmoc
icdmcmiddmod
vAvAv
vAvAv
+=+=
−
−
Onde,
Ganho de modo diferencial(Adm):
��
���
� +−−==
= 222211211
0
AAAAvv
Aicvid
oddm
Ganho de modo comum(Acm):
��
���
� +++==
= 222211211
0
AAAAvv
Aidvic
occm
![Page 41: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/41.jpg)
Ganho de modo diferencial para modo comum(Adm-cm):
��
���
� −+−===
− 422211211
0
AAAAvv
Aicvid
occmdm
Ganho de modo comum para modo diferencial(Acm-dm):
22211211
0
AAAAvv
Aidvid
oddmcm −−+==
=−
![Page 42: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/42.jpg)
• Em amplificadores diferenciais com simetria perfeita os termos Acm-dm e Adm-cm são nulos. No entanto, não significa que Acm será nulo. Neste caso defini-se a razão Adm/Acm com uma figura de mérito para medir a qualidade do amplificador diferencial, que é denominada razão de rejeição de modo comum ( CMRR - commom-mode-rejection ratio):
• Nos amplificadores práticos não se consegue uma simetria perfeita, Acm-dm≠0 e Adm-cm≠0. Define-se neste caso as razões
Adm /Acm-dm e Adm /Adm-cm como figura de mérito.
cm
dmAA
CMRR ≡
![Page 43: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/43.jpg)
– Característica de pequenos sinais para um amplificador diferencial balanceado.
• Em amplificador perfeitamente balanceado: Acm-dm=0 e Adm-cm=0
![Page 44: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/44.jpg)
ro→∞ e rb =0
![Page 45: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/45.jpg)
– Cálculo do ganho de modo diferencial• Sendo o circuito perfeitamente balanceado e as entradas iguais
e com sinais opostos:
πriv
Ricvb
idid .2
0==
=
22id
mod v
Rgv −=
Rgvv
A mvid
oddm
ic
−===0
0≠or orRR ||=Se →
![Page 46: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/46.jpg)
• Cálculo do ganho de modo comum
![Page 47: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/47.jpg)
![Page 48: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/48.jpg)
– Aproximação (meio circuito):
( )TAILm
mcm Rg
RgA
2..21+−≅
( )( )TAILvb
icic Rr
iv
Rid
2100
++===
βπ
![Page 49: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/49.jpg)
– Pelo princípio da superposição:
Ric
Ric
Rid/2Rid/2
Rx= Rid || (-2Ric) ≅ Rid
Ry= Ric/2-Rid/4 ≅ Ric
EEm RgCMRR ⋅⋅+= 21
![Page 50: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/50.jpg)
• Efeitos do descasamento de dispositivos nos amplificadores diferenciais
![Page 51: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/51.jpg)
• Tensão de Offset de entrada:
– Para zerar a tensão de offset na saída tem-se que aplicar um tensão na entrada:
021 =+− BEBEID VVV
���
����
�=��
�
����
�−���
����
�=
1
2
2
1
2
2
1
1 lnlnlnS
S
C
CT
S
CT
S
CTID I
III
VII
VII
VV
( ) ( ) 11
2
11
2
1 AVQDqn
AVWN
DqnI
CBB
ni
CBBA
niS == ( ) ( ) 2
2
2
22
2
2 AVQDqn
AVWN
DqnI
CBB
ni
CBBA
niS ==
1
2
2
1
C
C
C
C
RR
II =
��
�
����
����
����
����
����
����
�=
)()(
ln2
1
1
2
1
2
CBB
CBB
C
CTOS VQ
VQAA
RR
VV
![Page 52: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/52.jpg)
– Solução aproximada,
Considerando e a aproximação
21 XXX −=∆
221 XX
X+=
���
���
�
∆−=
∆+=
2
2
2
1
XXX
XXX
����
�
�
�
����
�
�
����
�
�
∆−
∆+
����
�
�
����
�
�
∆+
∆−
����
�
�
����
�
�
∆+
∆−=
2
2
2
2
2
2lnB
B
BB
CC
CC
TOS QQ
AA
AA
RR
RR
VV
BBCCCC QQRRRR <<∆<<∆<<∆ ,,
( ) �−+−=+<<
!3!21ln
321 xxxx
x
���
����
� ∆+∆−∆−≅B
B
C
CTOS Q
QAA
RR
VV
( ) mVVOS 5.105.001.0026.0 ≅+≅
S
S
II∆−
![Page 53: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/53.jpg)
• VOS drift
– Pode-se obter a valores de variação de offset com a temperatura na faixa de 1 µV/ºC.
���
����
� ∆+∆−∆−≅B
B
C
CTOS Q
QAA
RR
VV
TV
dTdV OSOS ≅ Ex: 2mV → 2mV/300ºK
→ 6.6 µV/ºC
![Page 54: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/54.jpg)
• Corrente de Offset de entrada
– Negligenciando os termos de ordem superiores
Desvio de 10% para beta e de 1% para resistores:
2
2
1
1
F
C
F
COS
III
ββ−=
����
�
�
����
�
�
∆−
∆−−∆+
∆+=
2
2
2
2F
F
CC
FF
CC
OS
II
II
I ββββ
���
����
� ∆+∆−≅ →���
����
� ∆−∆≅∆−=∆
F
F
C
C
F
COS
RR
II
F
F
C
C
F
COS R
RII
III
I C
C
C
C
ββ
βββ
β
)(11.0 BOS II −=
![Page 55: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/55.jpg)
• Características de pequenos sinais de um amplificador diferencial desbanlaceado
gm1.v1
+
-vi1
+
-
R1 vo1
+
-
rtail
R2vo2
gm2.v2
+
-
+
-vi2v1 v2
+
-
![Page 56: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/56.jpg)
• Resistores Descasados
R1
+
_v1
i1
R2
+
_v2
i2
22221121
221121
RiRivvv
e
RiRivvv
c
d
+=+=
−=−=
Definindo id=i1-i2, ic=(i1+i2)/2, ∆R=R1-R2 e R = (R1+R2)/2:
422222
2222
RiRi
RR
ii
RR
ii
v
e
RiRiR
Ri
iR
Ri
iv
dc
dc
dc
c
cdd
cd
cd
∆+=��
���
� ∆−��
���
� −−��
���
� ∆+��
���
� +=
∆+=��
���
� ∆−��
���
� −−��
���
� ∆+��
���
� +=
![Page 57: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/57.jpg)
R
+
_
vd/2
id/2
ic.∆∆∆∆R/2
_
+
R
+
_
vc
ic
id/2.∆∆∆∆R/2
_
+
• Circuitos metades (diferencial (a) e modo comum (b)) representativos do par de resistores descasados
(a) (b)
![Page 58: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/58.jpg)
• Fonte de correntes controladas por tensão Descasadas
22221121
221121
vgvgiii
e
vgvgiii
mmc
mmd
+=+=
−=−=
Definindo vd=v1-v2, vc=(v1+v2)/2, ∆gm =gm1-gm2 e gm = (gm1+gm2)/2:
422222
2222
dmcm
dc
mm
dc
mm
c
cmdmd
cm
md
cm
md
vgvg
vv
gg
vv
gg
i
e
vgvgv
vg
gv
vg
gi
∆∆∆∆++++====��������
������������
���� −−−−��������
������������
���� ∆∆∆∆−−−−−−−−��������
������������
���� ++++��������
������������
���� ∆∆∆∆++++====
∆∆∆∆++++====��������
������������
���� −−−−��������
������������
���� ∆∆∆∆−−−−−−−−��������
������������
���� ++++��������
������������
���� ∆∆∆∆++++====
gm1.v1
i1 i2
gm2.v2
![Page 59: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/59.jpg)
• Circuitos metades (diferencial (a) e modo comum (b)) representativos do par de fontes descasadas
gm.vd/2
id/2
∆∆∆∆gm/2 .vc
gm.vc
ic
∆∆∆∆gm/2 .vd/2
(a) (b)
![Page 60: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/60.jpg)
• Meio circuito diferencial
• Meio circuito modo comum
vgm
+
- icv
+
-
R
22idm vg∆
+
-
+
- 22RiRd ∆
v ocv
2.rtail
Rci
2id
mv
g2idv
+
-
R
vgm
2
∆
+
-
+
-2R
iRc∆
2odv
2Rdi
![Page 61: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/61.jpg)
• Resultando,
tailm
mmtailm
mvid
oddm rg
RgR
grg
Rgvv
Aic
21222
0 +
∆∆−∆∆+−==
=
���
����
�
+∆+∆−==
=−
tailm
mm
vic
oddmcm rg
RgRgvv
Aid
210
������������������������
����
����
����
++++
��������
����
����
��������
����
����
������������
����������������
���� ∆∆∆∆∆∆∆∆−−−−∆∆∆∆
++++∆∆∆∆−−−−============
−−−−tailm
m
mtailmmm
m
vid
occmdm rg
gg
rgRgRg
Rgvv
Aic
21
22
41
2
0
����
�
�
����
�
�
+
∆∆+∆−==
= tailm
mm
vic
occm rg
RgRg
vv
Aid
2122
0
![Page 62: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/62.jpg)
![Page 63: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/63.jpg)
![Page 64: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/64.jpg)
IEC/βR
ICC/βF
ICT
IC
IE
IB
IC = - IEC/βR + ICT
IE = - ICC/βF - ICT
IB = IEC/βR + ICC/βF
ICC - IEC
=
++
_
_
EM1 – Modelo Ebers-Moll 1
IEC=IS(eqVBC/kT-1)
ICC=IS(eqVBE/kT-1)
ICT=IS (eqVBE/kT-eqVBC/kT)
![Page 65: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/65.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.1 The basic MOS differential-pair configuration.
![Page 66: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/66.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.2 The MOS differential pair with a common-mode input voltage vCM.
![Page 67: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/67.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.3 Circuits for Exercise 7.1. Effects of varying vCM on the operation of the differential pair.
![Page 68: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/68.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.3 (Continued)
![Page 69: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/69.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.4 The MOS differential pair with a differential input signal vid applied. With vid positive: vGS1 > vGS2, iD1 > iD2, and vD1 < vD2; thus (vD2 − vD1) will be positive. With vid negative: vGS1 < vGS2, iD1 < iD2, and vD1 > vD2; thus (vD2 − vD1) will be negative.
![Page 70: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/70.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid = vG1 – vG2.
![Page 71: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/71.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2.
![Page 72: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/72.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.
![Page 73: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/73.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small-signal operation of the circuit.
![Page 74: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/74.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.9 (a) MOS differential amplifier with ro and RSS taken into account. (b) Equivalent circuit for determining the differential gain. Each of the two halves of the differential amplifier circuit is a common-source amplifier, known as its differential “half-circuit.”
![Page 75: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/75.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.10 (a) The MOS differential amplifier with a common-mode input signal vicm. (b) Equivalent circuit for determining the common-mode gain (with ro ignored). Each half of the circuit is known as the “common-mode half-circuit.”
![Page 76: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/76.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.11 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the gm values of Q1 and Q2.
![Page 77: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/77.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.12 The basic BJT differential-pair configuration.
![Page 78: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/78.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.13 Different modes of operation of the BJT differential pair: (a) The differential pair with a common-mode input signal vCM. (b) The differential pair with a “large” differential input signal.
![Page 79: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/79.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.13 (Continued) (c) The differential pair with a large differential input signal of polarity opposite to that in (b). (d) The differential pair with a small differential input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus Iremains constant with the change in vCM.
![Page 80: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/80.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure E7.7
![Page 81: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/81.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.14 Transfer characteristics of the BJT differential pair of Fig. 7.12 assuming α . 1.
![Page 82: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/82.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.15 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the linear range of operation can be extended) by including resistances in the emitters.
![Page 83: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/83.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.16 The currents and voltages in the differential amplifier when a small differential input signal vid is applied.
![Page 84: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/84.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.17 A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vid; dc quantities are not shown.
![Page 85: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/85.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.18 A differential amplifier with emitter resistances. Only signal quantities are shown (in color).
![Page 86: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/86.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.19 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier.
![Page 87: Amplificadores a Um e Dois Transistores](https://reader034.fdocumentos.tips/reader034/viewer/2022050920/5501cabd4a795971028b494d/html5/thumbnails/87.jpg)
Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.20 The differential amplifier fed in a single-ended fashion.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.21 (a) The differential half-circuit and (b) its equivalent circuit model.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.22 (a) The differential amplifier fed by a common-mode voltage signal vicm. (b) Equivalent “half-circuits” for common-mode calculations.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.23 (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode half-circuit.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.24 Circuit for Example 7.1.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.25 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the terminals with opposite polarity reduces VO to zero.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 7.26 (a) The BJT differential pair with both inputs grounded. Device mismatches result in a finite dc output VO. (b) Application of the input offset voltage VOS ; VO/Ad to the input terminals with opposite polarity reduces VO to zero.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.1 Two alternative representations of a signal source: (a) the Thévenin form, and (b) the Norton form.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.2 An arbitrary voltage signal vs(t).
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.3 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency v = 2pf rad/s.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.4 A symmetrical square-wave signal of amplitude V.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.8 Variation of a particular binary digital signal with time.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.20 Measuring the frequency response of a linear amplifier. At the test frequency v, the amplifier gain is characterized by its magnitude (Vo/Vi) and phase f.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.21 Typical magnitude response of an amplifier. |T(v)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(v) to the input Vi(v).
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.22 Two examples of STC networks: (a) a low-pass network and (b) a high-pass network.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.25 Circuit for Example 1.5.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure 1.27 Use of a capacitor to couple amplifier stages.
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Microelectronic Circuits - Fifth Edition Sedra/Smith Copyright 2004 by Oxford University Press, Inc.
Figure E1.23