A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in 0.35µm CMOS Technology

Fernando P. H. de Miranda Escola Politécnica

Universidade de São Paulo - Brasil Av. Prof. Luciano Gualberto, 158.

Trav.3 CEP: 05508-900 São Paulo - SP - Brasil.

(55)(11) 3091 9721 nando@lsi.usp.br

João Navarro S.Jr. Escola Politécnica

Universidade de São Paulo - Brasil Av. Prof. Luciano Gualberto, 158.

Trav.3 CEP: 05508-900 São Paulo - SP - Brasil.

(55)(11) 3091 5663 navarro@lsi.usp.br

Wilhelmus A.M. Van Noije Escola Politécnica

Universidade de São Paulo - Brasil Av. Prof. Luciano Gualberto, 158.

Trav.3 CEP: 05508-900 São Paulo - SP - Brasil.

(55)(11) 3091 5668 noije@lsi.usp.br

ABSTRACT The design of a dual modulus prescaler 32/33 in a 0.35µm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called Extended True Single Phase Clock (E-TSPC), an extension of the True Single Phase Clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

Categories and Subject Descriptors B.7.0 [Integrated Circuits]: General.

General Terms Design.

Keywords Prescaler, TSPC, High Speed Digital Circuit, Low Power

1. INTRODUCTION The CMOS Technology has been the main integrated circuit technology for at least 15 years due to its advantages in terms of integration level, power consumption, easiness of design, and low costs. With the continuous reduction of the transistor dimensions, some of these advantages, such as integration level, have increased and new ones have been added, such as the technology speed, extending the technology uses to areas where only faster and more expensive technologies (Bipolar and GaAs) were applicable.

One of these new application areas is RF circuits: circuits for transmission and reception of information through radio frequency waves. This area presents wide spectrum of applications varying from command devices for automatic gates to sophisticate cellular phones.

In the more complex RF systems, an important block is the frequency synthesizer. This block is responsible for the generation of signals in specific frequencies that are used for channel modulation and demodulation inside the transmission band [1]. A synthesizer is composed of a voltage controlled oscillator (VCO), counters, phase comparators, and filters. Some architectures of synthesizer use, with the counters, a dual-modulus prescaler N/N+1: a frequency divider that can divide an input clock by N or N+1. In general the prescaler is a block with critical operation in terms of speed and power consumption since it receives the clock directly from the VCO output, the fastest signal in the synthesizer.

In this work, we will present the design and simulation results of a dual-modulus prescaler 32/33. In the prescaler was used the E-TSPC technique, Extended True Single Phase Clock, that uses the True Single Phase Clock (TSPC, a logic technique that works with one clock phase [2]), and enlarges the acceptable design blocks and their possibility of connections [3], [4], [5]. Additionally, we applied some new structures that are conceived to duplicate the circuit speed [6]. The design was developed using the AMS 0.35 µm CMOS technology, with four levels of metal and two of polysilicon. The paper is organized in five sections: in section two the E-TSPC technique and the new structures are presented; in section three the prescaler 32/33 is discussed; in section four the results are drawn; in section five the conclusions are summarized.

2. THE E-TSPC TECHNIQUE The E-TSPC technique, an extension of the TSPC, was proposed in [4]. A simplified presentation, with respect to the theorems and their demonstrations, is done in [3], and it serves as basis to what is exposed here.

The following blocks are used for this technique: • complementary static logic gates CMOS; • dynamic, n-dynamic and p-dynamic, logic gates; • latches, n-latches and p-latches.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. SBCCI’04, Sept. 7-11, 2004, Porto de Galinhas, Pernanbuco, Brazil. Copyright 2004 ACM 1-58113-000-0/00/0004…$5.00.

Also N-MOS like blocks [5] can be used (see Figure 1). These blocks can be built starting from dynamic gates, n and p, or from latches, n and p. These blocks are faster although have higher power consumption, and they should be used when high speed is necessary.

In the technique the concept of data chains [6], n-data chains and p-data chains also is introduced. An n-data chain is a portion of the circuit that evaluates the input signals when the clock is at the HIGH level, and that holds the output value, with the last evaluated state, when the clock is at LOW level. The later state is called holding state and the former, evaluation state. In the case of p-data chains occurs the inverse of the n-data chains, being now the evaluation executed at the clock LOW level and the holding, at the HIGH level.

Formally we can define n-data chain as a data propagation path with the following characteristics:

1. must contain at least one n-dynamic block or n-latch; 2. must start in an external input of the circuit or in the output of some p-dynamic block or p-latch; 3. must contain only static, n-dynamic, or n-latches blocks; 4. do not matter the order or the number of these blocks; 5. must finish in the input of a p-dynamic block, or a p-latch, or be a circuit output.

Figure 1. Conversion of blocks to N-MOS like.

In the case of p-data chains, a similar definition can be applied, changing n for p and vice versa.

For the correct operation of a data-chain, to make the evaluation in one clock phase and the holding in the other, it is necessary that the data chain presents one of these two configurations:

• at least two blocks, one dynamic block and one latch; • at least two latches and an even number of blocks (inversions) between them.

Additionally, the adjacent blocks in the propagation path of a data-chain need to have a number of blocks (inversion) in accordance with the rules of table 1 (two blocks are called adjacent if between them there are placed only static blocks).

Examples of n-data chains are shown in Figure 2 [5] [6]: one n-data chain is initiated at the ia input and follows through the

blocks BA, BC, BE and BI; other n-data chain is initiated at the input id and follows through the blocks BC, BE, BF, BH and BK.

Some special data chains of the E-TSPC will be used to double the circuit speed. These data chains are called fo structures. To understand how they can be used, we must observe an operation characteristic of certain data chains [6]. Consider data chains, n or p, that possess a single latch (it must be, due to the rules, the last block of the data chain). For these data chains, called as fo-data chains (data chains with the fusible outputs), the output stays in a high impedance state during the holding state.

Table 1. Rule of the block connections inside of data-chains. N-MOS like blocks must obey the same rules of the normal

blocks

latch input

n-dynamic input

p-dynamic input

input signal of the data

chain n.r. n.r. n.r.

latch output n.r. n.a. n.a.

n-dynamic output n.r. odd n.a.

p-dynamic output n.r. n.a. odd

n.r.: no restrictions; n.a.: the connection is not allowed; odd: an odd number of blocks is required.

Figure 2. Examples of n-data chains.

This high impedance state in fo-data chains can be used to increase the processing speed, and implementations based on that are proposed. The outputs of two fo-data chains, a p and an n, can be joined and, in this case, we can get new processed signals to each half cycle of the clock, what implies in doubling the data output speed. Consider, for example, the circuit of Figure 3; during the phase where clock is HIGH, the n-data chain is in the evaluation state and imposes the result at the output, while the p-data chain will be in high impedance state; during the phase where the clock is LOW, the p-data chain is in evaluation and imposes the result at the output, while the n-data chain will be in high impedance. This type of structure is used in the proposed circuit.

p - t r a n s is . lo g ic

n - t r a n s is . lo g ic

in p u t o u tp u t

c lo c k

p - t r a n s is . lo g ic

n - t r a n s is . lo g ic

in p u t o u tp u t

c lo c k

p - t r a n s is . lo g ic

in p u t

o u tp u t

c lo c k

n - t r a n s is .lo g ic in p u t

o u tp u t

c lo c k

n - t r a n s is . lo g ic

in p u t

o u tp u t

c lo c k

c lo c k

n - t r a n s is . lo g ic

in p u t

o u tp u t

c lo c k

p - t r a n s is . lo g ic

in p u t

o u tp u t

c lo c k

c lo c k

p - t r a n s is .lo g ic

in p u t

o u tp u t

c lo c k

a ) n -d y n a m ic d ) N M O S l ik e

p -d y n a m ic c ) p -d y n a m ic b ) N M O S l ik e

n -d y n a m ic

e ) n - la tc h h ) N M O S l ik e

p - la tc h g ) p - la tc h f ) N M O S l ik e

n - la tc h

Figure 3. Fo Structures to duplicate the output data rate.

3. CIRCUIT DUAL-MODULUS PRESCALER 32/33 Figure 4 presents a conventional dual-modulus prescaler 32/33 circuit. It receives a clock signal and divides by 32 or 33, depending on the value of an external control signal called SM: when SM is at LOW logic level, the circuit divides the clock by 32 (N); when SM is at HIGH logic level, it divides the clock by 33 (N+1). This circuit is composed of two counters, a synchronous counter and an asynchronous counter. In the crosshatched part we find the synchronous counter that carries out the counting up to 4 or 5, depending on the value of the signal div8. The synchronous counter constitutes the critical element for good performance in terms of speed, since it receives as its clock the signal from the VCO output and, thus, works in the highest speed of the system. The asynchronous part is composed of three D type flip-flops (D-FF) that carry out the counting up to 8. It is the synchronous counter that generates the clock for the first D-FF of the asynchronous counter.

Figure 4. The Dual-Modulus Prescaler schematic (divider by

32/33). The implementation proposed here for the prescaler is based on a new synchronous counter circuit. This circuit is in fact a state machine and, similar to any state machine, it can be implemented with the fo-data chains previously defined. The desired output of the circuit, the clock divided by 4 or 5, is the state machine output and will be produced by the combination of two other signals, which are generated with a rate equal to the half of the clock rate.

The new implemented synchronous counter works as the state machine whose diagram is in figure 5, and its clock, clk/2, has a frequency equal to the half of the original clock frequency (the clock that we desire to divide by 4 or 5). The output is formed from the combination of signals A and B: A during the phase where clk/2 is HIGH and B during the phase where clk/2 is LOW. We can exemplify the operation analyzing the state diagram of figure 5. When the logic value at the div8 (division control signal) is HIGH, there are two possible operations for the state machine: to be moving between states 000 and 110, or between 100 and 010. Let us consider the case of moving between 000 and 110. The output signal will have the values LOW, A, LOW, B, HIGH, A, and HIGH, B (0011) during each half cycle of the clk/2. If we remember that the circuit works with half of the original clock

signal rate, we can see that the AB combination is the original clock signal divided by 4. When the logical value in div8 is LOW, the states will pass through the following states: 000, 110, 001, 010 and 101 and the output will have the values LOW, A, LOW, B, HIGH, A, HIGH, B, LOW, A, LOW, B, LOW, A, HIGH, B, HIGH, A, and LOW, B, (0011000110), during each half cycle of the clk/2. In this case we can see that AB combination is the clock signal divided by 5.

any value

Operation of the divider

by 4

any value

Counter output

000 110

001

010 100

101

111 011 1

0

0 1

1

0

State ABC

input div8

Temporary state

signal A e B

OU signal Asignal B

Counter output

sinal div8 signal A

signal B Counter output

signal div8

clock/2 signal = state machine clock

Clock signal

Operation of the divider by 5

Figure 5. State diagram of the circuit.

Figure 6 presents the schematic diagram of the state machine that implements the Figure 5 state diagram, and Figure 7 presents the transistor diagram of the complete synchronous counter for the AMS 0.35 µm technology (the transistor dimensions are also indicated). For the circuit implementation, TSPC D-FFs [2] (similar to Figure 8 D-FFs) modified in accordance with the E-TSPC rules have been applied. The logic gates NOR and AND have been merged with D-FFs, forming the three blocks marked in the Figure 7 (BLA, BLB and BLC). In addition to these blocks, we have two more, BLO1 and BLO2, that are responsible for merging the A and B signals.

Figure 6. Schematic diagram for implementation of the state

machine of the figure 5. In the asynchronous counter configuration TSPC D-FFs (Figure 8) were used. This counter presents a less critical operation in terms of speed.

Some comments must be done regarding the circuit transistor dimensions:

in2 out

p-data chain

p-data chain

fo-n data chain

n-data chain

fo-p data chain

in1

D-FFD Q

div8

clk/2

State Machine

A

BC

D-FF D Q D-FF

D Q

BLA BLC BLB

Q D

D-FF clock

div8

D C

Q Q output

32/33

sm

Divider by 4/5 (counter)

D D-FF

D D-FF Q Q

D C

Q Q D-FF

D C

Q Q D-FF D-FF

• in most transistors, the minimum width value allowed in the technology, W=1µm, was used. With this choice we favor a low power consumption and sacrifice the speed;

• in N-MOS like blocks, where N and P transistors need obey certain relations, dimensions different from the minimum were applied.

BLC

clk/2 clk/2 clk/2

div8

clk/2 clk/2

clk/2 clk/2

clk/2

clk/2 clk/2

clk/2

1.7

clk/2 clk/2

clk/2

clk/2 1.4

1.3 1.55

3.0

1.0

clk/2

clk/2

3.0

1.0

1.0

1.0

1.0

1.0

1.0

2.0

3.0

1.0

1.0

1.0

4.0

4.0

4.0

1.0

1.0

1.0

3.0

1.0

1.0

3.0 3.0

1.5 3.0

1.0

1.0

1.5

1.0

1.0 2.0 2.0

1.0

1.0 1.0

1.0 1.0

1.0 3.0

C A B

clock of the divide by 8

counter

clk/2

1.0

clk/2

clk/2

BLA BLB

BLO1 BLO2

Figure 7. Transistor diagram of the new synchronous counter implementation. The width dimension of the transistors, W,

are indicated in the figure. All the channel lengths are equal to the minimum of the technology (L=0.35µm).

The critical node in the circuit, in terms of speed, is the C node (see Figure 7). At this point, a relatively large load capacitance is present.

Figure 8. Configuration of TSPC D flip-flops (D-FF) for the asynchronous circuit. The transistor widths are indicated in

the figure (the length is 0.35 µm).

4. RESULTS The complete layout of the dual-modulus prescaler 32/33 circuit was implemented in a 0.35 µm CMOS technology. The circuit occupies an area of 65µm x 38µm and is presented in Figure 9.

Several simulations based on the netlist extracted from the layout were carried out. These simulations have been done through the program HSPICE, using BSIM3v3 model with typical (Ty) and slow (Sl) foundry parameters. In order to evaluate the proposed prescaler, the simulation results are compared with simulation results of a conventional prescaler, figure 4, implemented with E-TSPC blocks (without fo structures) in the same technology 0.35µm [1] and, later, with results from other prescalers presented in literature.

The graphics in Figure 10, Operation Frequency versus Power supply, in Figure 11, Power consumption versus Operation Frequency (for different power supply values), and in Figure 12, Power consumption versus Operation Frequency (for VDD = 3.3V

with Typical and Slow transistor parameters) present the simulation results of the proposed and the conventional prescaler implementations.

Figure 9. Layout of the new dual modulus prescaler 32/33. The circuit has the dimensions of 65µm x 38µm.

Figure 10. Operation frequency versus Power supply (Typical

model). The power consumption of each point is also indicated.

In Figure 10, we can observe that the proposed circuit is faster than the conventional circuit, being 900 MHz faster for VDD of 3 V. Notice that the power consumption in the proposed implementation is higher for the same power supply conditions due to the fact that in such conditions it works at a higher frequency.

Figure 11. Power consumption versus Operation frequency

(for different values of power consumption and Typical model). The power supply of each point is also indicated.

1.0

1.0

1.0

1.0

1.0

1.0

3.0

1.0

1.0

PD= 4.3

PD=3.31 mW

PD=1.84 mW

PD=0.91 mW

PD=0.26 mW

PD=0.24 mW

PD=1.46 mW

PD=2.55 mW

PD=3.37

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 0.5

1

1.5

2

2.5

3

3.5

4

Power Supply (V)

Operation Frequency (GHz)

new(Ty)old(Ty)

PD=0.69 mW

0.5 1 1.5 2 2.5 3 3.5 40

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Operation Frequency (GHz)

PowerConsumption(mW)

new (Ty) old (Ty)

VDD=3.3V

VDD =3.3V VDD =3.0V

VDD =3.0V

VDD =2.5V VDD =2.5V

VDD =2.0V VDD =2.0V

VDD =1.5V

In Figure 11, we can observe that, if the power supply could be adjusted, the proposed prescaler consumes less power for the same operation frequencies. As the power supply value is reduced, this advantage deteriorates, indicating that the new circuit is less effective at low power supply conditions.

In Figure 12, the behavior of the new and the conventional circuits are observed for Typical and Slow parameters. Analyzing the curves for typical parameters, we observe that for frequencies above 2 GHz the conventional circuit consumes lower power than the new one; however the new circuit can reach higher operation frequencies. For operation frequencies below this value, the situation changes, favoring the new implementation in all aspects. Analyzing the curves for slow model, similar conclusions can be drawn: for operation frequencies above 1.5 GHz, the conventional circuit consumes lower power, however the new circuit presents higher operation frequency. For operation frequencies below this value, the situation changes.

Figure 12. Power consumption versus Operation frequency (for VDD = 3.3V, using Typical and Slow model).

For a better evaluation of the proposed circuit, results from literature of different prescaler implementations are presented in table 2.

Two implementations pointed out in table 2 are particularly interesting: the prescaler of [5], a 132/133 dual modulus, is similar to the implementation called here as conventional version and uses a 0.8µm technology; the prescaler of [6], a 132/133 dual modulus, is similar to the implementation of this work and uses 0.8µm technology. Additionally, both [5] and [6] implementations were done with small width transistors. Comparing the results in table 2 we can find some important results:

• the implementation in [5] shows that the E-TSPC technique produces high speed and low power consumption circuits;

• the implementation in [6] and in this new work show that the new fo structures increase the speed of the prescaler without additional power costs;

• the speed improvement from the conventional to the new implementations in a 0.35 µm technology is similar to the speed improvement from the conventional, [5], to the new

implementations, [6], in a 0.8 µm technology (comparing simulations only). This indicates that the improvements do not really depend on the technology;

• the power consumption obtained in 0.35 µm technology is very low. This indicates that the circuit is excellent for low power applications.

Table 2 – Different prescaler performance from the literature. The crosshatched results are from simulations

* For this circuit, it is not clear if the measured power consumption includes or not the clock buffer power.

5. CONCLUSION In the transmission and reception of RF signals, an important block is the dual-modulus divide by N/N+1 prescaler. This divider is applied in the design of frequency synthesizers that generates different frequency signals used in transceivers.

In this work was proposed a 32/33 divider, implemented with the E-TSPC technique, an extension of the TSPC that considers new topologies, using new configurations of logic gates and registers, and with structures that allow doubling the speed at the data-chain output. The proposed prescaler combine high speed and low power consumption. From the simulation results we obtained an operation frequency of 4 GHz and power consumption of 4.4 mW, at 3.3V power supply in a 0.35 µm CMOS technology.

6. ACKNOWLEDGMENTS We thank CNPq and FAPESP for their partial support for this work.

Prescaler Tech.

(µm)

Power supply

(V)

Maximum frequency

(GHz)

Power consump. (without

clock buffer)(mW/GHz)

5 3

1.59 0.78

8.0 3.5

[5]

0.8 5 3

1.46 0.81

11.2 3.9

[6] 0.8 5 3

2.19 1.35

- -

[7] 0.8 5 3

1.22 0.64

20.9 9.3

[8] 0.8 5 3

1.8 1.34

29.4 -

[9] 0.8 3 1.3 7.5

[10] 0.7 5 3

2.65 1.75

- 13.7*

Conven. divider [1] 0.35 3 2.86 0.89

divider of this paper 0.35 3 3.74 0.88

0.5 1 1.5 2 2.5 3 3.5 41

1.5

2

2.5

3

3.5

4

4.5

Operation Frequency (GHz)

new (Ty)old (Ty)

new (SI)old (Sl)

Power Consumption (mW)

7. REFERENCES [1] Argüello. A.M.G. Estudo e Projeto de um sintetizador de

freqüência para RF em tecnologia CMOS de 0,35µm. Ms. Dissertation, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil, 2003 (in portuguese)

[2] Yuan, J.-R and Svensson. C. High speed CMOS circuit technique. IEEE J. Solid-State Circuits, 24, 1 (Feb 1989), 62-70.

[3] Navarro, J. and Van Noije, W. E-TSPC: Extended True Single Phase Clock CMOS circuit technique for high speed applications. SBMICRO J. Solid-State Devices and Circuits, 5, 2 (1997), 21-26.

[4] Navarro, J. Técnicas para projetos de ASICs CMOS de alta velocidade. PhD. Thesis, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil. 1998 (in portuguese).

[5] Navarro, J. and Van Noije, W. A 1.6-GHz dual modulus prescaler using the Extended True-Single-Phase-Clock CMOS circuit tecnique (E-TSPC). IEEE J. Solid-State Circuits. 34, 1 (Jan. 1999), 97-102.

[6] Navarro, J., and Van Noije, W. Extended TSPC structures with double input/output data throughput for Gigahertz CMOS circuit design. IEEE Trans. on VLSI Systems, 10, 3 (June 2002), 301-308.

[7] Chang, B., Park, J., and Kim, W. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. IEEE J. Solid-State Circuits, 31, 5 (May 1996), 749-752.

[8] Yang, C.-Y., Dehng, G.-K., Hsu, J.-M., and Liu, S.-I. New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid-State Circuits, 33, 10 (Oct. 1998), 1568-1571.

[9] Yan, H, Biyani, M., O, K. K. A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2 latch and its application in a dual-modulus prescaler. IEEE J. Solid-State Circuits, 34, 10 (Oct. 1999), 1400-1404.

[10] Craninckx, J., and Steyaert. M.S.J. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7 µm CMOS. IEEE J. Solid-State Circuits, 31, 7 (July, 1996), 890-897.