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Circuitos Lógicos e Organização de Computadores
Capítulo 5 – Representação Numérica e Circuitos Aritméticos
Ricardo [email protected]
http://docentes.puc-campinas.edu.br/ceatec/pannain/
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Conversão Decimal-Binária
2
3
Números em diferentes Bases
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Meio somador (Half-adder)
Sum s
0
1
1
0
Carry c
0
0
0
1
0 0 +
0 1 +
1 0 0 0
1 0 +
1 0
1 1 +
0 1
x y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
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Adição Binária
X x 4 x 3 x 2 x 1 x 0 =
Y + y 4 y 3 y 2 y 1 y 0 =
Generated carries
S s 4 s 3 s 2 s 1 s 0 =
15?? ??10
10?? ??10
25?? ??10
0 1 1 1 1
0 1 0 1 0
1 1 1 0
1 1 0 0 1
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SomadorCompleto
(Full-adder)
0 0 0 1 0 1 1 1
c i 1 +
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
c i x i y i
00 01 11 10
0
1
x i y i c i
1
1
1
1
s i x i y i c i ? ? ? ?=
00 01 11 10
0
1
x i y i c i
1
1 1 1
c i 1 + x i y i x i c i y i c i + + =
c i
x i
y i s i
c i 1 +
(a) Truth table
(b) Karnaugh maps
(c) Circuit
0 1 1 0 1 0 0 1
s i
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Implemantação de um Somador Completo usandodecomposiçãos
HAHAs
c c
c i x i y i
c i 1 +
s i
c i
x i y i
c i 1 +
s i
(a) Block diagram
(b) Detailed diagram
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Somador de n-bits tipo ripple-carry
FA
x n – 1
c n c n 1 ”
y n 1 –
s n 1 –
FA
x 1
c 2
y 1
s 1
FAc 1
x 0 y 0
s 0
c 0
MSB position LSB position
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Formatos para representação de números inteiros
b b bn 1– 1 0
Magnitude
MSB
(a) Unsigned number
bn 1– b1 b0
MagnitudeSign
(b) Signed number
bn 2–
0 denotes1 denotes
+– MSB
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Números inteiros sinalizados com 4 bits
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Exemplos de adição em complemento de 1
++1 1 0 0
1 0 1 00 0 1 0
0 1 1 1
0 1 0 10 0 1 0
++0 1 1 1
1 0 1 01 1 0 1
0 0 1 0
0 1 0 11 1 0 1
11
0 0 1 1
11
1 0 0 0
2+( )5–? ?
3-? ?+
5–? ?
7–? ?+ 2–? ?
5+( )2+( )7+( )
+
5+( )
3+( )+ 2–? ?
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Exemplos de adição em complemento de 2
++
1 1 0 1
1 0 1 10 0 1 0
0 1 1 1
0 1 0 10 0 1 0
++
1 0 0 1
1 0 1 11 1 1 0
0 0 1 1
0 1 0 11 1 1 0
11
ignore ignore
5+( )2+( )
7+( )
+
5+( )
3+( )
+ 2–? ?
2+( )5–? ?
3–? ?
+
5–? ?
7–? ?
+ 2–? ?
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Exemplos de subtração em complemento de 1
–0 1 0 10 0 1 0
5+( )2+( )
3+( )
–
1
ignore
+
0 0 1 1
0 1 0 11 1 1 0
–1 0 1 10 0 1 0–
1
ignore
+
1 0 0 1
1 0 1 11 1 1 0
5–? ?
7–? ?
2+( )
–0 1 0 11 1 1 0
5+( )
7+( )
– +
0 1 1 1
0 1 0 10 0 1 02–? ?
–1 0 1 11 1 1 0– +
1 1 0 1
1 0 1 10 0 1 02–? ?
5–? ?
3–? ?
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Interpretação Gráfica de números de 4 bits emcomplemento de 2
00000001
0010
0011
0100
0101
0110
01111000
1001
1010
1011
1100
1101
1110
1111
1 + 1 –2 +
3 +
4 +
5 +
6 + 7 +
2 –3 –
4 –
5 –
6 –7 – 8 –
0
8
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Somador / Subtrator
s 0 s 1 s n 1 –
x 0 x 1 x n 1 –
c n n -bit adder
y 0 y 1 y n 1 –
c 0
Add ??Sub control
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Exemplo de ocorrência de overflow
++
1 0 1 1
1 0 0 10 0 1 0
1 0 0 1
0 1 1 10 0 1 0
7+( )2+( )
9+( )
+
++
0 1 1 1
1 0 0 11 1 1 0
0 1 0 1
0 1 1 11 1 1 0
7+( )
5+( )
+ 2–? ?
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c4 0=c3 1=
c4 0=c3 0=
c4 1=c3 1=
c4 1=c3 0=
2+( )7–? ?
5–? ?
+
7–? ?
9–? ?
+ 2–? ?
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Somador de n-bits tipo ripple-carry
FA
x n – 1
c n c n 1 ”
y n 1 –
s n 1 –
FA
x 1
c 2
y 1
s 1
FAc 1
x 0 y 0
s 0
c 0
MSB position LSB position
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Somador ripple-carry com generação/propagação de sinais
x 1 y 1
g 1 p 1
s 1
Stage 1
x 0 y 0
g 0 p 0
s 0
Stage 0
c 0 c 1 c 2
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Somador carry-lookahead
Como fazer com que um somador trabalhe mais rápido ?
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Somador carry-lookahead com ripple-carry entre blocos
Block
x31 24–
c32 c24
y31 24–
s31 24–
x15 8–
c16
y15 8–
s15 8–
c8
x7 0– y7 0–
s7 0–
c03Block
1Block
0
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Dois estágios de um somador carry- lookahead
x 1 y 1
g 1 p 1
s 1
x 0 y 0
s 0
c 2
x 0 y 0
c 0
c 1
g 0 p 0
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Um somador hierárquico carry-lookahead
Block
x 15 8 – y 15 8 – x 7 0 – y 7 0 –
3 Block
1 Block
0
Second-level lookahead
c 0
s 7 0 –
P 0 G 0 P 1 G 1 P 3 G 3
s 15 8 –s 31 24–
c 8 c 16c 32
x 31 24– y 31 24–
c 24
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Projeto alternativo para um somador carry- lookahead
x 1 y 1
g 1 p 1
s 1 s 0
c 2
x 0 y 0
c 0
c 1
g 0 p 0
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Esquemático usando um módulo LPM adder/subtractor
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Resultado da simulação de um módulo LPM adder/subtrator
Optimized for cost
Optimized for speed
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Código VHDL para um full-adder
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY fulladd ISPORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;END fulladd ;
ARCHITECTURE LogicFunc OF fulladd ISBEGIN
s <= x XOR y XOR Cin ;Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
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Código VHDL para um somador de 4 bits
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY adder4 ISPORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout , x => x3, y => y3, s => s3 ) ;END Structure ;
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Declaração de um Package
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
PACKAGE fulladd_package ISCOMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;END fulladd_package ;
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Usando um package para somador de 4 bits
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;
ENTITY adder4 ISPORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;
BEGINstage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout , x => x3, y => y3, s => s3 ) ;END Structure ;
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Somador de 4 bits usando sinais multibit
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;
ENTITY adder4 ISPORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 ISSIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
BEGINstage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
END Structure ;
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Código VHDL code para um somador de 16-bit
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;
ENTITY adder16 ISPORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;END adder16 ;
ARCHITECTURE Behavior OF adder16 IS BEGIN
S <= X + Y ;END Behavior ;
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Somador de 16-bit com carry e overflow
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;
ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ;
ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
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Use of the arithmetic Uso de package com circuito aritmético
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;
ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;
X, Y : IN SIGNED(15 DOWNTO 0) ;S : OUT SIGNED(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ;
ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ;
BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
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Um somador de 16-bit adder usando sinais INTEGER
ENTITY adder16 ISPORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ;
S : OUT INTEGER RANGE -32768 TO 32767 ) ;END adder16 ;
ARCHITECTURE Behavior OF adder16 IS BEGIN
S <= X + Y ;END Behavior ;
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Circuito multiplicador 4 X 4
?
1 1 1 0
1 1 1 01 0 1 1
1 1 1 00 0 0 0
1 1 1 0
1 0 0 1 1 0 1 0
Multiplicand MMultiplier Q
Product P
(14)(11)
(154)
(a) Multiplication by hand
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?
1 1 1 0
1 1 1 01 0 1 1
1 1 1 0
1 0 0 1 1 0 1 0
Multiplicand MMultiplier Q
Product P
(11)(14)
(154)
+
1 0 1 0 10 0 0 0+
0 1 0 1 01 1 1 0+
Partial product 0
Partial product 1
Partial product 2
(b) Implemantação da multiplicação em hardware
Circuito multiplicador 4 X 4
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0
0
0
p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0
q 2
q 1
q 3
q 0
m 3 m 2 m 1 m 0 0
PP1
PP2
(a) Structure of the circuit
m k
q j
c in
Bit of PPi
FAc out
(c) A block in the bottom two rows
m k
q 1
c inFAc out
(b) A block in the top row
q 0
m k 1 +
Circuito multiplicador 4 X 4
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Multiplicação de números sinalizados
0 0 0 1 1 1 0
0 1 1 1 0 0 1 0 1 1
0 0 1 1 1 0
0 0 1 0 1 0 10 0 0 0 0 0
Multiplicand MMultiplier Q
Product P
(+14) (+11)
(+154)
+
+
0 0 0 1 0 1 0 0 0 1 1 1 0+
0 0 1 0 0 1 1 0 0 0 0 0 0+
0 0 1 0 0 1 1 0 1 0
Partial product 0
Partial product 1
Partial product 2
Partial product 3
(a) Positive multiplicand
x
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??
1 1 1 0 0 1 0
1 0 0 1 0 0 1 0 1 1
1 1 0 0 1 0
1 1 0 1 0 1 1 0 0 0 0 0 0
Multiplicand MMultiplier Q
Product P
( 14)(+11)
( 154)
+
+
1 1 1 0 1 0 1 1 1 0 0 1 0 +
1 1 0 1 1 0 0 0 0 0 0 0 0+
1 1 0 1 1 0 0 1 1 0
Partial product 0
Partial product 1
Partial product 2
Partial product 3
–
–
(b) Negative multiplicand
Multiplicação de números sinalizados
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Padrão IEEE 754 standard número de ponto flutuante
(c) Double precision
Sign
32 bits
23 bits of mantissa excess-127exponent
8-bit
52 bits of mantissa 11-bit excess-1023exponent
64 bits
Sign
S M
S M
(a) Single precision
E
+
E
0 denotes –1 denotes
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Código BCD – Binary Code Decimal
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Adição em BCD
+
1 1 0 0
0 1 1 10 1 0 1+
XY
Z
+75
120 1 1 0+
1 0 0 1 0carry
+
1 0 0 0 1
1 0 0 01 0 0 1+
XY
Z
+89
170 1 1 0+
1 0 1 1 1carry
S = 2
S = 7
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Somador BCD de um dígito – diagrama de blocos
4-bit adder
Detect if
MUX
4-bit adder
sum 9 >
6 0
X Y
Z
c out
c incarry-out
Adjust
S
0
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LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;
ENTITY BCD ISPORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;END BCD ;
ARCHITECTURE Behavior OF BCD ISSIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ;SIGNAL Adjust : STD_LOGIC ;
BEGINZ <= ('0' & X) + Y ;Adjust <= '1' WHEN Z > 9 ELSE '0' ;S <= Z WHEN (Adjust = '0') ELSE Z + 6 ;
END Behavior ;
Somador BCD de um dígito – código VHDL
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Simulação de um somador BCD de um dígito
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Circuito para um somador BCD de um dígitox x x x y y y y
c out
Four-bit adder
Two-bit adder
s 3 s 2 s 1 s 0
z 3 z 2 z 1 z 0
3 2 1 0 3 2 1 0
c in
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