Musa Iscas08 Slides

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A Passive Filter Aided Timing

Recovery Scheme

Faisal A. Musa, Anthony Chan Carusone

Department of Electrical and Computer Engineering

n vers y o oron o



• Introduction

• Baud-rate timing recovery (TR) schemes

•

• Measurement Results• Conclusions

2



Timing Recovery Techniques

CDR

(e.g. non-linear

spectral line)

Linear Non-linear or Bang-bang

(e.g. Hogge)

Baud-rateEdge-sampled

(focus of this work)

3



Analog Signal

Processor Front-End

Timing

Information

4

Edge-sampled Baud-Rate



• Wh baud-rate over ed e-sam led?

1. Reduced clock sampling phasesresults in less ower in the VCO andphase detector.

2. Better erformance in the resence ofISI and random noise.[F. Musa and A. Chan Carusone,``Modeling and Design ofMultilevel Ban -ban CDRs in the Presence of ISI and

Noise,’’ IEEE Transactions on Circuits and Systems I: RegularPapers, Vol. 54, No. 10, October 2007.]

5



-

• -

-.

. -

. -recovery [This work]

6



-• Integrating Front-End Based PD

Emami-Ne estanak A. Palermo S. Hae-Chan Lee Horowitz M.

VLSI Symposium 2004] :

7

• PD requires specific 4-bit patterns



-• Mueller-Muller Timing Recovery

. .

[ ])()(2

11 bk bk k k k k T hT h A A X A X −−+≈− −− τ τ

8

• True only for uncorrelated random data



-• MMSE PD based CDR (This work):

])}([{][ 22k bk k k kT y A E e E E τ +−==

eek k MMSE updates theMMSE updates the

sam lin hase,sam lin hase, ττ

to minimize eto minimize ek k 22::

k edE ][2

eek k 22

k bk k

k k k

kT dye

d

τ μ τ

τ

)(2

1

++=

−+

9

ττk k

k



-

eek k

⎤⎡ + k bkT dy τ )(

⎦⎣+k

k k k d τ 1

10

-



-

More robust than other baud-rate

constraints on the input data.

• Disadvantages:

equ res s ope an error n orma on.

11



- -

eek k

⎥⎦

⎤⎢⎣

⎡ ++=+

k

k k bbk k

d

kT dye

τ

τ θ τ τ

)(sgn]sgn[1

⎥⎦

⎤⎢⎣

⎡ +++≈

k

k k bbk

d

kT dykT y

τ

τ τ θ τ

)(sgn)](sgn[ ⎥

⎦⎢⎣

+++≈+

k

k k bbk k

d kT dykT yτ

τ τ θ τ τ )()(sgn1

12



- - ⎤⎡ + k kT dy τ )(

⎥⎤

⎢⎡ +

++≈

⎦⎣+

k k bbk

k

k bbk k

kT dykT y

d

τ τ θ τ

τ

)(sgn)](sgn[

1

⎥⎦

⎤⎢⎣

⎡ +++≈+

k

k k bbk k

d kT dykT yτ

τ τ θ τ τ )()(sgn1

k

This work

13



Integrate& Dump

LossyIntegrators

Data∫npu

CLKIntegrate and Dump

aided Slope Detector

∫

∫

Input

a

SlopeCLK

Data

(b) Active Filter aided

Slope Detector

Input

Data

(c)

Slope

Passive Filter aided Slope Detector

14

[This work]



• For 10-Gb/s data, the

me cons an was

chosen to be 10ps:R = 200 Ω, C = 50 fF

DataInput

Slopef

1/2πRC >> 0.5f bit

15



• Inductors improve

bandwidth withoutcompromising the

re a ve p ase s

between the data and

slope paths.

16



0.18 μm CMOS; Die area=1.1 mm2

17



Network Analyzer Measurements:

Data Path Bandwidth (Measured)=6-GHz.

18

.



DATA PATH OUTPUT

SLOPE PATH OUTPUT

19



• External Timing Recovery:

20



21



• A assive filter that rovides simultaneous low- assand high-pass characteristics was presented.

• The high-pass transfer characteristic is utilized to-

pass data output.

• Data and slope signals from the passive filter can be

timing recovery.

• Prototype passive filter was used with external

components to recover a - z c oc rom a - s231-1 random data sequence.

22



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