BUFFER DIFERENCIAL PARA PADS DE CIRCUITOS INTEGRADOS...
Transcript of BUFFER DIFERENCIAL PARA PADS DE CIRCUITOS INTEGRADOS...
BUFFER DIFERENCIAL PARA PADS DE CIRCUITOS
INTEGRADOS COM PROCESSO DE FABRICACAO DE 180 nm
Joao Vıtor Ferreira Duarte
Projeto de Graduacao apresentado ao Curso
de Engenharia Eletronica e de Computacao
da Escola Politecnica, Universidade Federal
do Rio de Janeiro, como parte dos requisitos
necessarios a obtencao do tıtulo de Enge-
nheiro.
Orientador: Fernando Antonio Pinto
Baruqui
Rio de Janeiro
Setembro de 2018
BUFFER DIFERENCIAL PARA PADS DE CIRCUITOS
INTEGRADOS C01vI PROCESSO DE FABRICA~AO DE 180 nm
Joao Vitor Ferreira Duarte
PROJETO DE GRADUAQAO SUBlVIETIDO AO CORPO DOCENTE DO CURSO
DE ENGENHARIA ELETRONICA E DE COivfPUTAQAO DA ESCOLA PO
LITECNICA DA UNIVERSIDADE FEDERAL DO RIO DE JANEIRO COMO
PAR'TE DOS REQUISITOS NECESSARIOS PARA A OBTENQAO DO GRAU
DE ENGENHElRO ELETRONICO EDE C01\1IPUTAQAO
Au tor:
Orientador:
ito Baruqui, D. Sc.
Examinador:
Prof. Carlos Fernando Teoclosio Soares , D. Sc.
Examinador:
Rio de Janeiro
Setembro de 2018
11
Declarac;ao de Autoria e de Direitos
Eu; Joa,o Vitor .Ferreira Duarte CPF 122.326.837-37, autor da monografia
buff er d'iferencial para pads de C'ircuitos integrados com processo de fabrica~:do de
180 nm, subsc:revo para os clevidos fins : as seguintes informa<;oes:
1. 0 autor declara que o trabalho apresentado na disc:iplina de Projeto de Gra
duatjao da Escola Politecnica da UFRJ e de sua autoria, sendo original em forma e
conte1J.do.
2. Excetuam-se do item 1. eventuais transcric;oes de texto, figuras, tabelas, conceitos
e icleias, que iclentifiquem claramente a fonte original, explicitando as autorizac;oes
obtidas dos respec:tivos proprietArios, quando nec:essarias.
3. 0 a.utor pennite que a UFRJ, por um prazo indeterminaclo, efetue em qualquer
m1dia de divulgac;a.o, a publica<;iio do trabalho academico em sua totalidade, ou em
parte. Essa autorizac;ao nao envolve onus de qualquer natureza a UFRJ , OU aos seus
representantes.
4. 0 autor pode, excepcionalmente, enc:aminhar a Comissiio de Projeto de Gra
dua<;ii.o, a na.o divulga<;iio do material, por um prazo maximo de 01 (um) ano,
improrrogavel, a c:ontar da data de defesa, desde que o pedido seja justificado, e
solicitado antecipadamente, por escrito, a Congregac;iio da Escola Politecnica.
5. 0 autor declara, aincla, ter a capacidade juddica para a pratica do presente ato;
assim como ter conhecimento do teor da presente Declarac;iio, estando ciente das
sarn;oes e punic;oes legais, no que tm1ge a c6pia parcial, ou total, de obra intelec:tual;
o que se configura como violac;ao do direito autoral previsto no C6digo Penal Bra
sileiro no art.184 e art.299, bem como na Lei 9.610.
6. 0 autor e o mico responsavel pelo c:onte1do apresentado nos tra.balhos academicos
publicados, nao cabendo a UFRJ, a.os sens representantes, OU ao(s) orientador(es),
qualquer responsabiliza<;ao/ indeniza<;a.o nesse sentido.
7. Por ser verdade, firmo a presente declarac;ao.
lll
UNIVERSIDADE FEDERAL DO RIO DE JANEIRO
Escola Politecnica - Departamento de Eletronica e de Computacao
Centro de Tecnologia, bloco H, sala H-217, Cidade Universitaria
Rio de Janeiro - RJ CEP 21949-900
Este exemplar e de propriedade da Universidade Federal do Rio de Janeiro, que
podera incluı-lo em base de dados, armazenar em computador, microfilmar ou adotar
qualquer forma de arquivamento.
E permitida a mencao, reproducao parcial ou integral e a transmissao entre bibli-
otecas deste trabalho, sem modificacao de seu texto, em qualquer meio que esteja
ou venha a ser fixado, para pesquisa academica, comentarios e citacoes, desde que
sem finalidade comercial e que seja feita a referencia bibliografica completa.
Os conceitos expressos neste trabalho sao de responsabilidade do(s) autor(es).
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AGRADECIMENTO
Agradeco primeiramente ao meu orientador, Prof. Baruqui, por ter me ajudado
tanto ao longo deste trabalho e ao Prof. Pietro Maris por ter me proposto este
projeto.
Agradeco ao laboratorio de processamento analogico e digital de sinais (PADS)
por ter fornecido a infraestrutura - licencas de software e computadores para as
simulacoes - para realizacao deste trabalho.
Agradeco tambem a Andrey Takashi Ishikiriyama por ajudar com a revisao do
texto em ingles.
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RESUMO
Este trabalho propoe uma topologia de buffer diferencial para sistemas embar-
cados, que e capaz de operar em grandes variacoes de temperatura (de -40 C a
175 C), podendo ser utilizado para interfacear sinais internos do chip atraves de
pads do circuito integrado, levando em conta os efeitos de capacitancia parasita. O
projeto consiste em realizar o design do esquematico, desenho de layout e simulacoes
pos-layout, utilizando um processo de fabricacao de 180 nm da X-Fab.
Palavras-Chave: buffer, microeletronica, temperatura, sistemas embarcados
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ABSTRACT
This work proposes a differential buffer topology for embedded systems, that is
capable of sustaining a high temperature variation (from -40 C to 175 C), being
able to interface internal signals from the chip through the pads of the integrated
circuit, taking into account the effects of parasitic capacitance. The project consists
in designing the schematic, drawing the layout and making post-layout simulation,
using a 180 nm process from X-Fab.
Key-words: buffer, microelectronics, temperature, embedded systems
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SIGLAS
AC - Alternating Current
ADAS - Advanced Driving Assistance Systems
AM - Amplitude Modulation
CAD - Computer Assisted Design
CMOS - Complementary Metal Oxide Semiconductor
CMRR - Commom-Mode Rejection Rate
DC - Direct Current
DDA - Differential Difference Amplifier
FDA - Fully Differential Amplifier
GEEPS - Laboratoire de Genie Electrique et Electronique de Paris
LP - Low Pass
NMOS - N-channel Metal Oxide Semiconductor
OTA - Operational Transconductance Amplifier
PADS - Laboratorio de Processamento Analogico e Digital de Sinais
PMOS - P-channel Metal Oxide Semiconductor
SNR - Signal to Noise Ratio
THD - Total Harmonic Distortion
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Contents
1 Introduction 1
1.1 Theme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Project’s Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Introduction to Differential Buffers 5
2.1 Advantages of the Fully Differential Design . . . . . . . . . . . . . . . 8
2.1.1 Noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Even-Order Harmonics cancellation . . . . . . . . . . . . . . . 9
2.1.3 Higher peak-to-peak Output . . . . . . . . . . . . . . . . . . . 9
3 Buffer Topology 10
3.1 Base Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Differential Unbalanced Pair . . . . . . . . . . . . . . . . . . . 11
3.1.2 Common-Mode Feedback Circuit . . . . . . . . . . . . . . . . 13
3.1.3 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Temperature Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Adapting to Our Specifications . . . . . . . . . . . . . . . . . . . . . 14
3.4 Final Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Schematic Design 16
4.1 Basic Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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4.2.1 Unbalanced Differential Amplifier . . . . . . . . . . . . . . . . 17
4.2.2 Common-Mode Feedback Block . . . . . . . . . . . . . . . . . 18
4.2.3 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.4 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Schematic Simulation Results 21
5.1 Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.1 Gain x Vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.2 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.3 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Monte Carlo Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2 Gain and Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.3 Input-Referred Noise . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.4 Common-Mode Output Voltage . . . . . . . . . . . . . . . . . 32
6 Layout 36
6.1 Common-Mode Feedback Block . . . . . . . . . . . . . . . . . . . . . 36
6.1.1 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.2 Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.3 Output Transistors . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2.1 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2.2 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . 41
6.2.3 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3 Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7 Post-layout simulation 43
7.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.1 Gain x Vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.2 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1.3 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . 46
7.1.4 THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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7.1.5 Gain and Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1.6 Input-Referred Noise . . . . . . . . . . . . . . . . . . . . . . . 51
7.1.7 Common-Mode Output Voltage . . . . . . . . . . . . . . . . . 52
8 Conclusion 55
8.1 Analysis of the results . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Bibliography 58
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List of Figures
2.1 Differential Difference Amplifier Component . . . . . . . . . . . . . . . . 6
2.2 Differential Difference Amplifier With Feedback Loop . . . . . . . . . . . 7
2.3 Fully Differential Buffer With Noise at Inputs . . . . . . . . . . . . . . . 8
3.1 Original Buffer Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Schematic of Unbalance Differential Pair . . . . . . . . . . . . . . . . . . 11
3.3 Graph of gm in the Unbalanced Pair . . . . . . . . . . . . . . . . . . . . 12
3.4 Buffer Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Common Mode Feedback Block Schematic . . . . . . . . . . . . . . . . . 15
4.1 Flowchart of the Design Workflow . . . . . . . . . . . . . . . . . . . . . 16
5.1 Test Bench Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Schematic Results - DC Sweep . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Schematic Results - Derivative of DC sweeped output . . . . . . . . . . . 23
5.4 Schematic Results - AC Sweep Analisys . . . . . . . . . . . . . . . . . . 24
5.5 Schematic Results - Transient Analysis . . . . . . . . . . . . . . . . . . . 25
5.6 Schematic Results - Transient Analysis with stability test . . . . . . . . . 26
5.7 Schematic Results - THD parametric sweep . . . . . . . . . . . . . . . . 27
5.8 Schematic Results - Monte Carlo THD @ 27 C . . . . . . . . . . . . . . 28
5.9 Schematic Results - Monte Carlo THD at Maximun and Minimin Temper-
atures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.10 Schematic Results - Monte Carlo Gain @ 27 C . . . . . . . . . . . . . . 29
5.11 Schematic Results - Monte Carlo Gain at Maximun and Minimin Temper-
atures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.12 Schematic Results - Monte Carlo Phase @ 27 C . . . . . . . . . . . . . . 30
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5.13 Schematic Results - Monte Carlo Phase at Maximun and Minimin Tem-
peratures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.14 Schematic Results - Monte Carlo Input-Referred Noise @ 27 C . . . . . . 32
5.15 Schematic Results - Monte Carlo Input-Referred Noise at Maximun and
Minimin Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.16 Schematic Results - Monte Carlo Common-Mode Output Voltage @ 27 C 33
5.17 Schematic Results - Monte Carlo Common-Mode Output Voltage at Max-
imun and Minimin Temperatures . . . . . . . . . . . . . . . . . . . . . . 34
5.18 Schematic Results - Monte Carlo Output Disparity @ 27 C . . . . . . . . 35
5.19 Schematic Results - Monte Carlo Output Disparity at Maximun and Min-
imin Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Layout - Common-Mode Feedback Circuit Layout . . . . . . . . . . . . . 37
6.2 Layout - Interdigitated Transistors Pattern . . . . . . . . . . . . . . . . 38
6.3 Layout - Common Centroid Pattern with 16 transistors . . . . . . . . . . 39
6.4 Layout - Buffer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.5 Layout - Common Centroid Pattern with 10 transistors . . . . . . . . . . 40
6.6 Layout - Common Centroid Pattern with two centroids . . . . . . . . . . 41
6.7 Layout - Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Post-Layout Results - DC Sweep . . . . . . . . . . . . . . . . . . . . . . 44
7.2 Post-Layout Results - Derivative of DC sweeped output . . . . . . . . . . 44
7.3 Post-Layout Results - AC Sweep Analisys . . . . . . . . . . . . . . . . . 45
7.4 Post-Layout Results - Transient Analysis with stability test . . . . . . . . 46
7.5 Post-Layout Results - THD parametric sweep . . . . . . . . . . . . . . . 47
7.6 Post-Layout Results - Monte Carlo THD @ 27 C . . . . . . . . . . . . . 48
7.7 Post-Layout Results - Monte Carlo THD at Maximun and Minimin Tem-
peratures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.8 Post-Layout Results - Monte Carlo Gain @ 27 C . . . . . . . . . . . . . 49
7.9 Post-Layout Results - Monte Carlo Gain at Maximun and Minimin Tem-
peratures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.10 Post-Layout Results - Monte Carlo Phase @ 27 C . . . . . . . . . . . . 50
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7.11 Post-Layout Results - Monte Carlo Phase at Maximun and Minimin Tem-
peratures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.12 Post-Layout Results - Monte Carlo Input-Referred Noise @ 27 C . . . . . 51
7.13 Post-Layout Results - Monte Carlo Input-Referred Noise at Maximun and
Minimin Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.14 Post-Layout Results - Monte Carlo Common-Mode Output Voltage @ 27 C 53
7.15 Post-Layout Results - Monte Carlo Common-Mode Output Voltage at
Maximun and Minimin Temperatures . . . . . . . . . . . . . . . . . . . 53
7.16 Post-Layout Results - Monte Carlo Output Disparity @ 27 C . . . . . . . 54
7.17 Post-Layout Results - Monte Carlo Output Disparity at Maximun and
Minimin Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 Gain vs Differential Input in Different Temperatures . . . . . . . . . . . 55
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List of Tables
4.1 Transistor Sizes - Differential Amplifier . . . . . . . . . . . . . . . . . 18
4.2 Transistor sizes - Common-Mode Rejector . . . . . . . . . . . . . . . 18
4.3 Transistor Sizes - Common-mode output/input mirrors . . . . . . . . 18
4.4 Transistor Sizes - Bias Current Mirrors . . . . . . . . . . . . . . . . . 19
4.5 Transistor Sizes - Parameters of the output stage . . . . . . . . . . . 19
5.1 Schematic Results - AC Sweep Results . . . . . . . . . . . . . . . . . 24
5.2 Schematic Results - THD results from Monte Carlo Simulation . . . . 27
5.3 Schematic Results - Gain and Phase results from Monte Carlo Simu-
lation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 Schematic Results - Input-Referred Noise . . . . . . . . . . . . . . . . . 31
5.5 Schematic Results - Common-Mode Output Voltage . . . . . . . . . . . . 33
5.6 Schematic Results - Output Disparity . . . . . . . . . . . . . . . . . . . 34
7.1 Post-Layout Results - AC Sweep Results . . . . . . . . . . . . . . . . 45
7.2 Schematic Results - THD results from Monte Carlo Simulation . . . . 47
7.3 Post-Layout Results - Gain and Phase results from Monte Carlo Sim-
ulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.4 Post-Layout Results - Input-Referred Noise . . . . . . . . . . . . . . . . 51
7.5 Post-Layout Results - Common-Mode Output Voltage . . . . . . . . . . . 52
7.6 Post-Layout Results - Output Disparity . . . . . . . . . . . . . . . . . . 53
8.1 Summary of the Results . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Chapter 1
Introduction
1.1 Theme
This work is the final project for the undergraduate course of electronics and com-
puter engineering at Universidade Federal do Rio de Janeiro (UFRJ). It is mainly
related to the embedded electronics field, specially, the analog microelectronics de-
sign.
The main theme of this work is to study and develop a differential integrated
buffer, that was based on the topology suggested in the previous work[1].
The aim of this work is to adapt the circuit proposed in [1], to make the buffer
capable of operating the interface between the internal circuits of the chip and the
output pads – being able to isolate the signal and drive the parasitic capacitance
of it –, and them to solve the problem of instrumentation with high temperature
ranges, by proposing an architecture that holds its characteristics, such as linearity,
gain and output voltage swing, under a wide temperature range.
1.2 Project’s Scope
The purpose of this work is to develop a basic building block for analog micro-
electronics design. Starting from a known topology that was initially proposed as
an AM demodulator manufactured in a 0.35 µm process and adapt it to operate
1
with a different process, the XH018 from X-Fab, that is a 0.18 µm process aimed to
embedded electronics devices.
This project can be used in more complex systems for different applications, and it
is restricted to the schematic definition as well as layout and post-layout simulations.
Implementation in silicon will be left for the future and we will not address it in this
phase of the project.
The work was developed in partnership with PADS - UFRJ and GEEPS - Uni-
versite Paris-Saclay.
1.3 Justification
With the growth of ADAS (Advanced Driving Assistance Systems) and autonomous
driving, the demand for reliable integrated designs is also driven up, as those sys-
tems have tight validation requirements and need an excellent reliability to be used
in real world scenarios as well as a high energy efficiency; this project intend to fulfill
this need by designing a reliable low power fully differential buffer.
The main purpose of this buffer is to interface internal signals from the integrated
circuit to an external environment, e.g. for sampling the output of a pressure sen-
sor. Although the design was made thinking in automotive electronics, and it is
also possible to use this same design in generic embedded electronics for different
applications, where the system is operating in high temperature ranges and needs
high linearity.
1.4 Objectives
The objective is to make the buffer reliable in a wide range of temperature, in
this work we chose the corner cases for this technology from -40 C to 175 C. It
means that it should keep most of its characteristics and operate as a buffer at this
temperature range.
2
The two main performance parameters that we used to design this circuit were
the gain and the output voltage swing. The output voltage swing is defined as the
maximum voltage range (peak-to-peak) that the buffer delivers at the output while
keeping the total harmonic distortion in an acceptable level.
The major goal was to deliver a high output swing, being at least 1 VPP , while
using a supply voltage of 1.8 V, under the temperature variation that we are working
with. We also aimed to have this buffer operating with a 3 MHz frequency, so the
cut-off frequency was placed at least 1 decade higher, to have a gain closer to 1.
As secondary objectives, we tried to minimize the distortion, the thermal noise
and the area, but in principle there were no strict restrictions to those parameters.
1.5 Methodology
We designed this circuit following a common workflow in microelectronics, which
will be further detailed in Chapter 4. It basically starts from the requirements and
goes to the schematic design, and after its validation, we can start drawing the
layout using CAD tools. When we are satisfied with the layout we can move on to
the last phase, that is the layout validation and adjust it to meet the requirements
if necessary.
Starting from the requirements, the schematic was designed using the design equa-
tions that are further detailed in Chapter 3. From this basic design, we have adopted
a more empirical methodology, by using the provided software design tools. It was
possible to make a more interactive design by making small changes and checking
its results. This opened the possibility for exploring different ideas throughout the
process.
We have used the same methodology for the layout design. After the whole circuit
was finished, we could make small adjustments until the requirements were fulfilled.
In order to validate both, schematic and layout, we used simulation tools.
3
1.6 Description
In Chapter 2, there will be a more theoretical introduction to differential buffers,
as well as the problem with the common mode and how we designed the buffer to
deal with it in a vast temperature range.
Following to the Chapter 3, we will present the architecture of the buffer that
inspired this study and how we adapted it in our specifications.
At Chapter 4, the methodology of the project will be more detailed, as well as the
final results of the schematic design. In Chapter 5, we will have more details about
the tests’ methodology and also the results of the schematic validation.
Chapter 6 will present the layout and the techniques used for reducing some effects
as temperature gradients and device mismatching, and the results of post-layout
simulations will be shown in Chapter 7.
In our last chapter, the conclusions and the discussion about the future work that
can be done from this study will be presented.
4
Chapter 2
Introduction to Differential
Buffers
This chapter will give a brief introduction on how differential buffers work and
some of the theory behind it. The basic differential buffer can be built based on
a fully differential operational transconductance amplifier (OTA). Most of CMOS
integrated circuits make use of this type of amplifiers, because of their simple con-
struction and their many applications (as comparators, oscillators, peak detectors,
etc). This type of amplifier is often proposed in literature, because of its perfor-
mance with respect to linearity, output swing and supply voltage. In addition, the
differential characteristic gives it a low sensitivity to some interferences, such as
external noise and even-order harmonics [2].
The buffer is a Differential Difference Amplifier (DDA)[3] and the basic idea is
that those amplifiers have two differential inputs and one differential output, as
shown in Figure 2.1, differently from the classic operational amplifier, that has two
single inputs, the inverting and non-inverting inputs, and one output.
Let Vin be the voltage difference between the positive and negative non-inverting
inputs, and V′in the equivalent for the inverting outputs. The output Vout will be
defined as:
Vout = AOL(Vin − V′
in) (2.1)
5
Figure 2.1: Differential difference amplifier component.
In (2.1), AOL is the Open Loop Gain. For an ideal operational amplifier, this
value of AOL tends to infinity. In the real world, those amplifiers have a AOL value
high enough to saturate the output voltage to either Vdd or Vss. In order to achieve
stability, it is necessary to add a feedback network. The Figure 2.2 shows an amplifier
with a negative feedback loop.
In this configuration, we apply a portion of the output voltage in the inverting
input, defined as βVout, with 0 < β ≤ 1 . This creates a negative feedback loop. In
this configuration the gain will be:
Vout = AOL(Vin − βVout) (2.2)
Vout(1 + βAOL) = VinAOL (2.3)
So the total gain for the negative feedback loop is:
AV =VoutVin
=AOL
1 + βAOL
(2.4)
If we use β = 1, it means a feedback loop of a short circuit between the output
and the inverting input, and considering the ideal value AOL to be infinity, the gain
in this case is:
6
Figure 2.2: Differential difference amplifier schematic with a feedback loop
represented by the β block.
AV = limAOL→∞
AOL
1 + AOL
= 1 (2.5)
This is the ideal buffer, but note that the gain will be in the order of 250 in more
realistic scenarios. In this case we have AV = 250251
= 0.996. This result is close
enough to 1 for most applications.
One drawback of using a fully differential architecture is that we have what it is
called “Common mode voltage” or Vcm. The common mode voltage is defined as:
Vcm =Vo+ + Vo−
2(2.6)
This voltage appears at the output as a DC source in series with an AC output
that represents the AC gain.
7
This topology has some advantages as: increased immunity to external noise;
increased output voltage swing; application in low voltage systems; reduced even-
order harmonics and others[4].
2.1 Advantages of the Fully Differential Design
2.1.1 Noise immunity
In a differential signal, external noise will affect both inputs of the system in the
same way. In Figure 2.3, we have a schematic of the buffer with two distinct input
sources (Vi+ and Vi−), as well as the noise source, modeled here as a DC source in
series with output voltage Vn(t).
The output voltage Vo will be defined as:
Vod = Vo+ − Vo− = (Vi+ + Vn)− (Vi− + Vn) = Vi+ − Vi− (2.7)
So this type of noise will not appear at the output of the system
Figure 2.3: Fully differential buffer with a noise source affecting both inputs.
8
2.1.2 Even-Order Harmonics cancellation
In realistic scenarios, due to intrinsic non-linearities of the systems, the input
will suffer some distortions, that will generate higher order harmonics in the output
signal.
Considering a perfectly matched differential buffer, meaning that both outputs
will have the same distortion and a sinusoidal differential input, using a generic
power expansion of the output we have:
Vo+ = k1Vin + k2V2in + k3V
3in + . . . (2.8)
Vo− = k1(−Vin) + k2(−Vin)2 + k3(−Vin)3 + . . . (2.9)
Where k1,2,3,... are arbitrary constants. The differential output will be:
Vod = Vo+ − Vo− = k1Vin + k3(−Vin)3 + . . . (2.10)
So, all the even-order harmonics will cancel out. This results in an overall decrease
of the Total Harmonic Distortion (THD)
2.1.3 Higher peak-to-peak Output
As the differential output is based in the difference between two voltages, we can
achieve a higher peak-to-peak ratio by using the difference between them.
9
Chapter 3
Buffer Topology
3.1 Base Architecture
The chosen topology of the buffer was based in [1] and it is shown at Figure 3.1;
This architecture can be segmented in four different blocks: two amplifiers using
a differential unbalanced pair; an output stage with folded-cascode output and the
common mode feedback loop.
Figure 3.1: Base buffer designed, as presented in [1].
To achieve the unity gain, the amplifiers were arranged to produce an internal
current feedback, creating a buffer. The following sections will detail each of those
10
three basic building blocks.
3.1.1 Differential Unbalanced Pair
In this topology, two identical asymmetric pairs are arranged as shown in Figure
3.2. Each differential amplifier have transistors with different aspect ratios, and
this asymmetry shifts the transconductance curve away from the center point. An
illustration of those curves is shown in Figure 3.3.
Figure 3.2: Schematic of unbalance differential pair using NMOS.
As those pairs are arranged in parallel, the resulting curve of those two amplifiers
is the sum of curves. The idea here is to use those two pairs to achieve a better
dynamic range with a higher linearity. Note that both curves shown in Figure 3.3
are symmetric in relation to a center point. By summing both of them, the result
will be a curve with higher dynamic range.
Defining gma(vd) = dia1/dvd and gmb(vd) = dib1/dvd, by the symmetry, we have
that gma(vd) = gmb(−vd). To force the equiripple condition, we need three maxi-
mums. This forces us to use gm0 = 2gm′0. The project equations can be obtained
by the following equations[1].
11
Figure 3.3: Graph of gm of the unbalanced pair.
gmd(−Vdmax) = gm0
gmd(−Vdmin) = gm0
gm0 = 2gm′0
(3.1)
IB = 1.05133× gm0Vdmax
βa = 14.3675× αgm0/Vdmax
βb = 1.51977× αgm0/Vdmax
(3.2)
Where α is a transistor parameter, βa and βb is the β parameter of each of the
transistors in the unbalanced pair, that can be used to determine the W/L ratio,
and gm0 is the transconductance of the transistor.
The maximum distortion in this cases occurs at 0.41 × Vdmax and it is equal to
2.34%.
12
3.1.2 Common-Mode Feedback Circuit
The common-mode feedback circuit works by sampling the common mode voltage
at the output and comparing it to a reference voltage. Then it will output a current
proportional to the error between those voltages and inject this current in the output
of both differential pairs in the buffer.
The basic idea is, when the common mode voltage in the output is higher than the
reference, we reduce the bias current in the differential pair, bringing the common
mode voltage down. If this voltage is higher than the reference, the circuit does the
opposite increasing the current. This creates a control loop that stabilizes when the
common mode voltage at the output is equal to the reference voltage.
3.1.3 Output Stage
The original article used a folded-cascode configuration, this gives us a better
stability and higher impedance, but it has a slightly worse output swing range than
a common source output.
In order to make this topology to work properly, a high open loop gain is necessary,
and the output stage was designed for sustaining a high gain with the desired peak-
to-peak output voltage. We opted to use a common source output instead of the
folded-cascode.
3.2 Temperature Analysis
The chosen topology helps us to mitigate temperature effects, as we use an internal
feedback loop with two symmetrical amplifiers. Given the output impedance Zo and
the transconductance gain gm, the output voltage of the buffer is given by:
Vo = Vo+ − Vo− = Zo × gm(Vin+ − Vin−)− Zo × gm(V0+ − Vo−) (3.3)
Assuming the output voltage Vo, the output impedance Zo and the transconduc-
tance gm as functions of the temperature, our output voltage will be:
13
Vo(T ) = Zo(T )gm(T )Vin − Zo(T )gm(T )Vo(T ) (3.4)
Vo(T ) + Zo(T )gm(T )Vo(T ) = Zo(T )gm(T )Vin (3.5)
Vo(T )
Vin=
Zo(T )gm(T )
1 + Zo(T )gm(T )(3.6)
If we can ensure that Zo(T )gm(T ) >> 1, our gain will be:
Vo(T )
Vin= 1 (3.7)
So, in this case, the gain of the buffer will not depend on the temperature, as long
as the product Zo(T )gm(T ) is much grater than 1.
3.3 Adapting to Our Specifications
One major difference that we made while adapting this architecture was to ex-
periment with PMOS, instead of the original NMOS architecture. This choice was
made in order to mitigate body effects, because we can connect the bulk directly to
the drain.
The other major change was to remove the cascode current mirrors and it drasti-
cally changed the output stage. Because of using a lower voltage, 1.8 V instead of
the original 3.5 V, the cascode mirror could not keep in the saturation state for the
1.2 VPP input, so we had to adapt to a single current mirror in order to compensate
for this problem.
The changes in the output stage were made to achieve the higher peak-to-peak
voltage in the output, as well as having a greater gain. The architecture of a Miller
operational amplifier was used to achieve this performance. As we have a higher
gain, the effects of temperature variation will be decreased, as shown in the previous
section.
14
For the common-mode feedback circuit, we have used the same topology of a pair
of two transistors with different W/L ratios, so the common mode can have a higher
sensitivity range.
3.4 Final Design
To make the layout simpler, we separated the circuit in two blocks, one with both
input and feedback OTA’s and the output stage and other with only the Common-
Mode Feedback stage. Those final schematics can be seen in figures 3.4 and 3.5.
Figure 3.4: Buffer Schematic.
Figure 3.5: Common-mode feedback block schematic.
15
Chapter 4
Schematic Design
This chapter will explain the methodology used in this work and will show the
final schematic design.
4.1 Basic Workflow
Figure 4.1 describes the workflow that was used. Starting from the initial speci-
fications, we started to design the circuit from there. We first started to design the
circuit at the schematic level. At each iteration, we went back to the layout design
to validate the design, by using the test suite that will be more detailed in Chapter
5. We could either validate it or go back and make changes in the layout, as shown
in the flowchart.
Figure 4.1: Flowchart describing the interactive workflow used throughout
this project.
16
In order to simplify the design, the buffer was divided into smaller blocks, which
could be designed and tested independently from each other. We first made an ideal
common-mode feedback block, so we could design the rest of the buffer. When we
were satisfied with the buffer, the common-mode feedback block was swapped from
a transistor implementation and them it could be designed independently from the
rest. The final validation step was made with buffer as a whole. This final validation
also included more sophisticated simulations, such as Monte Carlo analysis.
The layout design followed the same procedure. But in this case we started from
the common-mode feedback block, as it is a smaller block that could be tested
separately and them we went to drawing the rest of the buffer. At the end, it was
easier to make small adjustments to fix eventual problems with the layout.
In the end, we ran the same test bench for comparing how the performance was
degraded from the schematic design, were the software takes into account the tran-
sistor model, and the post-layout simulations, were parasitic resistors and capacitors
from the layout are also taken into account.
4.2 Schematic Design
This section will break-up the schematic into smaller blocks and showcase the
chosen sizes for each transistor.
4.2.1 Unbalanced Differential Amplifier
We start the project by the desired cut-off frequency, by using a generic approxi-
mation for the transfer function of the buffer, we have:
H1(s) =Vod(s)
Vid(s)≈ 1
s C0
gm0+ 1
(4.1)
In this approximation, the buffer acts as a low-pass filter with the cut-off frequency
being ω0 = gm0/C0. For our case we used C0 = 15 pF and ω0 = 50 MHz ×2π, which
leads to gm0 = 4.7× 10−3 S.
17
By using (3.2) and (3.1), and the parameters that are described in the Appendix
A, we can calculate the desired beta, thus the W/L ratio of the transistors.
The final values to our OTA are shown in Table 4.1.
Table 4.1: Transistor sizes in the differential amplifier.
Transistors Unity Width (W) Length (L) Fingers Multiplicy Total W/L
M8, M10, M12, M14 4 µm 1 µm 4 4 64
M9, M11, M13, M15 2 µm 2 µm 1 2 8
4.2.2 Common-Mode Feedback Block
As this block uses the same topology shown before (two differential unbalanced
pairs), we can use the same equations, but reducing the size and multiplicity, as we
don’t need a high cut-off frequency in this block. The common-mode voltage can
be considered as DC or low frequency.
Table 4.2: Transistor sizes of the common-mode sensor’s unbalanced amplifier.
Transistor Unity Width (W) Length (L) Fingers Multiplicy Total W/L
M24, M26, M28, M30 1 µm 0.5 µm 4 4 16
M25, M27, M29, M31 1 µm 0.5 µm 1 2 4
The output of this stage is transited to the main stage as a current injection using
the PMOS mirror. Those transistors were dimensioned to work as a current mirror
and match the bias current on each net. As the differential pair operates with a
higher current, it has a bigger size.
Table 4.3: Sizes of the transistors used in the common-mode output/input.
Transistor Unity Width (W) Gate Length (L) Fingers Multiplicy Total W/L
M32, M33 2 µm 1 µm 1 4 8
M18, M19 2 µm 1 µm 4 4 32
18
4.2.3 Current Mirrors
We started from a basic unity transistor size, that was L = 1 µm and W = 8 µm.
Them, they were dimensioned to match the desired current in each net. This mirror
was intended to work with a current Ibias = 120 µA. This value was chosen to achieve
the desired gm0 value. In the table below we show the number of fingers.
Table 4.4: Sizes of the transistors used for the current mirrors.
Transistor Fingers Multiplicity Ratio to Base Current
M1 1 8 1 120 µA
M2, M3, M4, M5 4 2 1 120 µA
M20, M21, M22, M23 1 2 1/4 30 µA
M6, M7 16 5 10 1.2 mA
The number of fingers and multiplicity were mainly chosen thinking in the layout
and it was designed to make easier to adopt topologies like common-centroid an of
interdigitated layout.
4.2.4 Output Stage
The transistors in this stage were designed to stay in the saturation region, while
holding an 1.2 VPP output. The pole split compensation was determined by simu-
lation. The select parameters for the transistors (M16 and M17) and the pole split
are:
Table 4.5: Parameters of the output stage.
Parameter Value
L 0.5 µm
W 165 µm
R 100 Ω
C 1.2 pF
19
The total width was spliced in 3 transistors with 5 fingers, where each unity
transistor had W = 11 µm
20
Chapter 5
Schematic Simulation Results
In this chapter we will present the methodologies that were used for the simula-
tions we performed as well as the test bench used to generate this results. Then
we will present the results from the simulations using the schematic. This means
that those results will take into account the behavior of the transistors used in this
process, but neglecting some parasitic effects from the layout.
5.1 Test Bench
The test bench is shown at Figure 5.1. We used an ideal 1.8 V DC voltage source
Vdd for the power supply and an ideal 120 µA DC current source to bias the current
mirrors.
We are using 15 pF capacitor to simulate the parasitic capacitance of each pad, one
at each output. For the input we use a single AC ideal voltage source coupled with
a DC ideal voltage source, then we use a built in component in Cadence Virtuoso to
generate a differential voltage with a DC common mode. We used a DC source in
series with a pulse generator as the reference voltage (Vref ), this voltage pulse was
used in some tests for stability analysis of the common mode feedback compensation.
21
Figure 5.1: Test Bench schematic.
5.2 Simulation Results
5.2.1 Gain x Vid
In this test, we made a DC sweep at the differential input voltage and measured
the differential output, while keeping the common mode voltage constant and equal
to 700 mV. The temperature was also kept at nominal value (27 C).
The result can be seen at Figure 5.2. In Figure 5.3 we have the derivative of this
differential output. Here we can see a high linearity and high dynamic range.
At 600 mV we got a slope of 0.997 for a 1.2 VPP output. If we use a lower range,
at 1 VPP , the slope becomes 0.999, being closer to the ideal buffer.
5.2.2 AC Analysis
In this simulation, the input signal was swept to determine the circuit response
in the frequency domain, keeping the input differential voltage constant at 1.2 VPP .
The buffer can be seen as a low-pass filter. As we can see in Figure 5.4, the cut-off
frequency is 60 MHz. After this point, we have a slope factor of about −35 dB/dec.
This means that we can approximate this buffer to a second-order LP filter. This
22
Vin diff Vout diff
V (
mV
)
-1000
-900.0
-800.0
-700.0
-600.0
-500.0
-400.0
-300.0
-200.0
-100.0
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000Name Vis
Vdc (m)-900.0 -700.0 -500.0 -300.0 -100.0 100.0 300.0 500.0 700.0 900.0
Vin diff:Vout diff Wed Apr 4 19:02:19 20181
Figure 5.2: Output differential voltage of a DC sweep simulation.
gm
0.62
0.64
0.66
0.68
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1.0
1.02Name Vis
Vdc (m)-900.0 -700.0 -500.0 -300.0 -100.0 100.0 300.0 500.0 700.0 900.0
gm Wed Apr 4 19:02:19 20182
Figure 5.3: Derivative of the output differential voltage in a DC sweep simu-
lation.
23
M1: 59.11679MHz -3.0dB
phase gain (dB)
V (
deg)
-340.0
-320.0
-300.0
-280.0
-260.0
-240.0
-220.0
-200.0
-180.0
-160.0
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
(dB
)
-65.0
-60.0
-55.0
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0Name Vis
freq (Hz)10
-210
-110
010
110
210
310
410
510
610
710
810
910
10
phase:gain (dB) Wed Apr 4 19:08:05 20181
Figure 5.4: Output of an AC sweep in the buffer.
approximation will be used furthermore in the noise analysis.
In this simulation we can also validate that the pole split compensator is able to
greatly reduce the overshoot.
One small drawback is that the phase is not equal to 0 degrees after 1 MHz. For
the proposed application, we use a frequency of 3 MHz, the following results use
this frequency, one decade higher and one decade lower:
Frequency Gain Phase
300 kHz 1.8 mdB -0.4
3 MHz 0.5 mdB -3.9
30 MHz -57.6 mdB -42.8
Table 5.1: Results of three points in the AC sweep analysis.
24
5.2.3 Transient Analysis
Figure 5.5 shows the results of the transient analysis with an sinusoidal input
signal with frequency of 4 MHz, amplitude of 1.2 VPP and common mode voltage of
0.7 V.
Vin diff Vout diff gain
V (
mV
)
-700.0
-600.0
-500.0
-400.0
-300.0
-200.0
-100.0
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
(T
)
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
95.0Name Vis
time (us)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Vin diff:Vout diff:gain Wed Apr 4 19:12:32 20181
Figure 5.5: Results of the transient analysis.
We can use this simulation to test the stability of the common mode compensation
module. For this test we injected a pulse of 1 V with width of 1 ms, and no instability
was observed, as seen in Figure 5.6.
25
/Vinp /Vinn /vcm /Vout+ /Vout- /I58/net070 /net031
V (
V)
0.3
0.38
0.46
0.54
0.62
0.7
0.78
0.86
0.94
1.02
1.1Name Vis
time (ms)0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
Transient Response Wed Apr 4 19:19:59 20182
Figure 5.6: Results from the stability test in the transient analysis.
5.3 Monte Carlo Analysis
This section shows the results from a Monte Carlo Analysis with 200 points and
3 temperatures: The nominal temperature (27 C), as well as the highest (175 C)
and the lowest (-40 C) supported temperatures for this process.
5.3.1 THD
THD (Total Harmonic Distortion), according to the following equation
THD =
√V 22 + V 2
3 + V 24 + . . .
V1× 100% (5.1)
Where V1 is the amplitude of the fundamental component and Vn is the amplitude
of the nth harmonic. In our case, as our topology greatly reduces the even harmonics,
26
we will only have the effects of the odd harmonics.
For our tests we used the function thd in Cadence. We first made a parametric
analysis of the THD with a 4MHz signal and a varying differential input voltage.
The result is shown at Figure 5.7. We can see that the optimal level is around 600
mV.
thd
(m
)
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0
600.0
650.0
700.0
750.0
800.0Name Vis
Vac (m)380.0 420.0 460.0 500.0 540.0 580.0 620.0 660.0 700.0 740.0 780.0 800.0
thd Tue Sep 11 10:56:39 20181
Figure 5.7: Parametric sweep of the THD (in percentage), from 400 mV to
800 mV
The results of the Monte Carlo simulation are shown in Table 5.2. The correspon-
dent histograms are shown in Figures 5.8, 5.9a and 5.9b
Temperature Mean σ
-40 C 0.18% 0.09%
27 C 0.08% 0.03%
175 C 0.06% 0.03%
Table 5.2: Results from the 3 differents corners in the Monte Carlo Simulation for
the THD
27
81.0023m
μ
46.5297m
-σ
115.475m
σ
12.0570m
-2σ
149.948m
2σ
-22.4156m
-3σ
184.420m
3σ
thd
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
40.0
42.0
44.0
46.0
48.0
Values (m)-30.0 -10.0 10.0 30.0 50.0 70.0 90.0 110.0 130.0 150.0 170.0 190.0 210.0 220.0
Number = 200Mean = 81.0023mStd Dev = 34.4727m
thd 1
Figure 5.8: Histogram of the Monte Carlo simulation of the THD at typical
temperature.
180.861m
μ
92.3245m
-σ
269.398m
σ
3.78794m
-2σ
357.934m
2σ
-84.7487m
-3σ
446.471m
3σ
thd_t min
No.
of S
ampl
es
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
Values (m)-100.0 -50.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0 550.0 600.0 650.0 700.0
Number = 200Mean = 180.861mStd Dev = 88.5366m
thd_t min 1
(a) Minimum Temperature (-40 C)
66.1887m
μ
35.8926m
-σ
96.4847m
σ
5.59658m
-2σ
126.781m
2σ
-24.6995m
-3σ
157.077m
3σ
thd_t max
No.
of S
ampl
es
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
Values (m)-30.0 -10.0 10.0 30.0 50.0 70.0 90.0 110.0 130.0 150.0 170.0 180.0
Number = 200Mean = 66.1887mStd Dev = 30.2960m
thd_t max 1
(b) Maximum Temperature (175 C)
Figure 5.9: Histogram of the Monte Carlo simulation of the THD at minimum (left) and
maximum (right) temperatures.
5.3.2 Gain and Phase
Running the same simulation for the gain and phase, at the 3 MHz output with
amplitude 1.2 VPP . The results are shown in Table 5.3, and the histograms are
28
present in Figures 5.10, 5.11a, 5.11b, 5.12, 5.13a and 5.13b.
TemperatureMean
(Gain)
σ
(Gain)Mean (Phase) σ (Phase)
-40 C 1.001 0.007 -4.8 0.1
27 C 1.001 0.006 -5.5 0.1
175 C 1.002 0.005 -6.7 0.2
Table 5.3: Results from the 3 differents corners in the Monte Carlo Simulation for
the gain and phase
1.00096
μ
994.617m
-σ
1.00730
σ
988.277m
-2σ
1.01364
2σ
981.937m
-3σ
1.01998
3σ
gain
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
40.0
42.0
44.0
46.0
48.0
50.0
Values0.976 0.98 0.984 0.988 0.992 0.996 1.0 1.004 1.008 1.012 1.016 1.02 1.024 1.026
Number = 200Mean = 1.00096Std Dev = 6.34013m
gain 1
Figure 5.10: Histogram of the Monte Carlo simulation of the Gain at typical
temperature.
29
1.00073
μ
993.448m
-σ
1.00801
σ
986.166m
-2σ
1.01530
2σ
978.884m
-3σ
1.02258
3σ
gain_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
40.0
42.0
44.0
46.0
48.0
50.0
Values0.97 0.975 0.98 0.985 0.99 0.995 1.0 1.005 1.01 1.015 1.02 1.025 1.03
Number = 200Mean = 1.00073Std Dev = 7.28234m
gain_t min 1
(a) Minimum Temperature (-40 C)
1.00180
μ
996.587m
-σ
1.00702
σ
991.371m
-2σ
1.01223
2σ
986.156m
-3σ
1.01745
3σ
gain_t max
No.
of S
ampl
es
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
Values0.982 0.986 0.99 0.994 0.998 1.002 1.006 1.01 1.014 1.018 1.022 1.024
Number = 200Mean = 1.00180Std Dev = 5.21573m
gain_t max 1
(b) Maximum Temperature (175 C)
Figure 5.11: Histogram of the Monte Carlo simulation of the Gain at minimum (left) and
maximum (right) temperatures.
-5.50886
μ
-5.62258
-σ
-5.39514
σ
-5.73630
-2σ
-5.28142
2σ
-5.85002
-3σ
-5.16770
3σ
phase
No.
of S
ampl
es
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
Values-5.95 -5.9 -5.85 -5.8 -5.75 -5.7 -5.65 -5.6 -5.55 -5.5 -5.45 -5.4 -5.35 -5.3 -5.25 -5.2 -5.15 -5.1 -5.05 -5.0
Number = 200Mean = -5.50886Std Dev = 113.719m
phase 1
Figure 5.12: Histogram of the Monte Carlo simulation of the phase at typical
temperature.
30
-4.85388
μ
-4.95668
-σ
-4.75109
σ
-5.05947
-2σ
-4.64829
2σ
-5.16226
-3σ
-4.54550
3σ
phase_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
Values-5.2 -5.15 -5.1 -5.05 -5.0 -4.95 -4.9 -4.85 -4.8 -4.75 -4.7 -4.65 -4.6 -4.55 -4.5
Number = 200Mean = -4.85388Std Dev = 102.794m
phase_t min 1
(a) Minimum Temperature (-40 C)
-6.70070
μ
-6.90465
-σ
-6.49675
σ
-7.10859
-2σ
-6.29281
2σ
-7.31254
-3σ
-6.08886
3σ
phase_t max
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
40.0
42.0
44.0
46.0
48.0
Values-7.4 -7.3 -7.2 -7.1 -7.0 -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 -6.2 -6.1 -6.0 -5.9 -5.8
Number = 200Mean = -6.70070Std Dev = 203.946m
phase_t max 1
(b) Maximum Temperature (175 C)
Figure 5.13: Histogram of the Monte Carlo simulation of the phase at minimum (left)
and maximum (right) temperatures.
5.3.3 Input-Referred Noise
Following the results of our AC analysis, there is approximately a −35 dB per
decade slope after the cut-off frequency. With this result, we can approximate our
buffer to a second order low pass filter.
Considering a ω3dB frequency of 60 MHz, the effective noise bandwidth can be
calculated according to the formula described in [5]:
ωnoise = ω3dB × 1.11 = 60 MHz× 1.11 = 66.6 MHz (5.2)
To reduce effects of low frequency flicker noise, we started our window from 10 kHz
to 66.6 MHz. The results are shown in Table 5.4.
Temperature Mean σ
-40 C 324.8 µV 5.4 µV
27 C 375.9 µV 6.8 µV
175 C 458.0 µV 9.0 µV
Table 5.4: Input-Referred Noise for three different temperatures.
31
The histograms are shown in Figures 5.14, 5.15a and 5.15b.
375.952u
μ
369.114u
-σ
382.791u
σ
362.275u
-2σ
389.629u
2σ
355.437u
-3σ
396.468u
3σ
Band noise
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (u)350.0 355.0 360.0 365.0 370.0 375.0 380.0 385.0 390.0 395.0 400.0 405.0
Number = 100Mean = 375.952uStd Dev = 6.83848u
Band noise 1
Figure 5.14: Histogram of the Monte Carlo simulation of the Input-Referred
Noise at typical temperature.
324.817u
μ
319.433u
-σ
330.202u
σ
314.048u
-2σ
335.586u
2σ
308.664u
-3σ
340.971u
3σ
Band noise_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
Values (u)304.0 308.0 312.0 316.0 320.0 324.0 328.0 332.0 336.0 340.0 344.0 348.0 350.0
Number = 100Mean = 324.817uStd Dev = 5.38451u
Band noise_t min 1
(a) Minimum Temperature (-40 C)
457.967u
μ
448.991u
-σ
466.943u
σ
440.015u
-2σ
475.919u
2σ
431.039u
-3σ
484.895u
3σ
Band noise_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Values (u)425.0 430.0 435.0 440.0 445.0 450.0 455.0 460.0 465.0 470.0 475.0 480.0 485.0 490.0 495.0
Number = 100Mean = 457.967uStd Dev = 8.97604u
Band noise_t max 1
(b) Maximum Temperature (175 C)
Figure 5.15: Histogram of the Monte Carlo simulation of the Input-Referred Noise at
minimum (left) and maximum (right) temperatures.
5.3.4 Common-Mode Output Voltage
For evaluating the effectives of the common-mode feedback circuit, we tested the
output common-mode voltage, defined as VCM = (Vo+ + Vo−)/2. For this test we
kept the input’s differential voltage as 0 V while keeping both common-mode input
32
and common-mode reference voltages at 700 mV. The results are shown in Table
5.5 and the histograms in Figures 5.16, 5.17a and 5.17b.
We can see that in all cases the common-mode feedback circuit works for com-
pensating the common-mode voltage.
Temperature Mean σ
-40 C 698.2 mV 4.8 mV
27 C 697.9 mV 4.7 mV
175 C 696.1 mV 4.6 mV
Table 5.5: Common-Mode Output Voltage for three different temperatures.
697.837m
μ
693.110m
-σ
702.563m
σ
688.384m
-2σ
707.289m
2σ
683.658m
-3σ
712.015m
3σ
Common Mode
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
Values (m)678.0 680.0 682.0 684.0 686.0 688.0 690.0 692.0 694.0 696.0 698.0 700.0 702.0 704.0 706.0 708.0 710.0 712.0 714.0 716.0
Number = 100Mean = 697.837mStd Dev = 4.72622m
Common Mode 1
Figure 5.16: Histogram of the Monte Carlo simulation of the Common-Mode
Output Voltage at typical temperature.
In the same test, we also evaluated the output disparity, defined as:
Vdisp = |Vo+ − Vo−| (5.3)
33
698.251m
μ
693.435m
-σ
703.067m
σ
688.619m
-2σ
707.883m
2σ
683.803m
-3σ
712.699m
3σ
Common Mode_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
25
Values (m)678.0 682.0 686.0 690.0 694.0 698.0 702.0 706.0 710.0 714.0 718.0
Number = 100Mean = 698.251mStd Dev = 4.81593m
Common Mode_t min 1
(a) Minimum Temperature (-40 C)
696.068m
μ
691.436m
-σ
700.700m
σ
686.805m
-2σ
705.331m
2σ
682.173m
-3σ
709.963m
3σ
Common Mode_t max
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (m)678.0 680.0 682.0 684.0 686.0 688.0 690.0 692.0 694.0 696.0 698.0 700.0 702.0 704.0 706.0 708.0 710.0 712.0 714.0
Number = 100Mean = 696.068mStd Dev = 4.63156m
Common Mode_t max 1
(b) Maximum Temperature (175 C)
Figure 5.17: Histogram of the Monte Carlo simulation of the Common-Mode Output
Voltage at minimum (left) and maximum (right) temperatures.
While keeping the same test conditions as before, with no differential voltage at
the input. In this case, both outputs should have the same voltage. This test is a
measure of how close the buffer is from the ideal scenario.
The results are shown in Table 5.6 and the histograms in Figures 5.18, 5.19a and
5.19b
Temperature Mean σ
-40 C 2.9 mV 2.2 mV
27 C 2.8 mV 2.2 mV
175 C 2.7 mV 2.1 mV
Table 5.6: Output Disparity for three different temperatures.
34
2.84626m
μ
634.860u
-σ
5.05766m
σ
-1.57654m
-2σ
7.26906m
2σ
-3.78794m
-3σ
9.48046m
3σ
output disparity N
o. o
f Sam
ples
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
Values (m)-4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12
Number = 100Mean = 2.84626mStd Dev = 2.21140m
output disparity 1
Figure 5.18: Histogram of the Monte Carlo simulation of the Output Dispar-
ity at typical temperature.
2.94827m
μ
659.648u
-σ
5.23689m
σ
-1.62897m
-2σ
7.52552m
2σ
-3.91760m
-3σ
9.81414m
3σ
output disparity_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
Values (m)-4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12
Number = 100Mean = 2.94827mStd Dev = 2.28862m
output disparity_t min 1
(a) Minimum Temperature (-40 C)
2.71838m
μ
621.438u
-σ
4.81533m
σ
-1.47551m
-2σ
6.91227m
2σ
-3.57245m
-3σ
9.00921m
3σ
output disparity_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Values (m)-4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12
Number = 100Mean = 2.71838mStd Dev = 2.09694m
output disparity_t max 1
(b) Maximum Temperature (175 C)
Figure 5.19: Histogram of the Monte Carlo simulation of the Output Disparity at mini-
mum (left) and maximum (right) temperatures.
35
Chapter 6
Layout
In the previous chapter, there were shown results from simulations using the
schematic. As those results were satisfactory for the proposed application, we went
to the next phase in the design flow, that is the layout.
In this chapter we will present the layout and the techniques used throughout
the design. As the layout is split in two main blocks, we will focus on each one
separately
The layout followed basically the same work-flow The circuit was split into two
blocks as was done with the schematic. By first the layout of the Common-Mode
Feedback was made and the parasitics were extracted, so we could validate its be-
havior independently of the rest of the circuit.
6.1 Common-Mode Feedback Block
The final layout for this block is shown in Figure 6.1. The basic building blocks of
the common-mode feedback circuit are the current mirrors for bias, the differential
pairs and the output stage. Each block will be detailed in the next topics.
36
Figure 6.1: Final layout of the common-mode feedback circuit.
37
6.1.1 Current Mirrors
The current mirrors were arranged in an interdigitated manner, as shown in Figure
6.2. This arrangement can reduce some effects as process and temperature gradients.
A common-centroid between the four transistors would have a greater reduction of
the temperature gradient effects, but would also increase layout complexity, even in
the expense of more area to make the connections.
Figure 6.2: Pattern used for the current mirror, using interdigitated transis-
tors.
This block was surround by a guard ring in order to reduce latch up effects.
6.1.2 Differential Pairs
The differential pairs were arranged in a common centroid pattern, as shown
in Figure 6.3. To reduce latch-up effects, each transistor was surrounded by an
individual guard ring.
This pattern can greatly reduce the effects of temperature gradients, in the two
dimensional plane. The same pattern was used for both amplifiers.
6.1.3 Output Transistors
As can be seen in Figure 3.5, the transistor M33 is used as a dummy in order to
balance the structure and M32 is the actual output, they weren’t put in any special
pattern. The choice was made mainly for reducing the overall area of the block.
38
Figure 6.3: Common Centroid Pattern with 16 transistors.
6.2 Differential Amplifier
The final layout is shown at Figure 6.4. The same applies here, this block is
basically composed by current mirrors, the unbalanced differential amplifiers and an
output stage. It also has the RC pair for the pole split compensation and current
mirrors to couple the the common mode rejection circuit.
6.2.1 Current Mirrors
For the current mirrors that are used to bias the Differential Amplifiers, the same
layout as shown in Figure 6.2 was used. For the output stage we used a common
centroid pattern as shown in Figure 6.5.
As the output stage have a higher current, we need to use bigger transistors. For
keeping the same unit size, those two transistors were split in 5. The used pattern
was chosen for using a better pairing between the two mirrors, in order to reduce
the disparity in the output.
39
Figure 6.4: Layout of the buffer part of the circuit.
Figure 6.5: Common centroid pattern with 10 transistors used in the current
mirrors for the output stage.
40
Figure 6.6: Common centroid pattern with two centroids and 4 transistors
(each one divided in four).
6.2.2 Differential Amplifiers
Those two amplifiers were designed with a slightly different common centroid
patter. The pattern shown in Figure 6.3 has proven to be harder to route with
bigger transistors. As those amplifiers operate in current mode, the tracks had to
be thicker.
By changing the pattern to the one shown in Figure 6.6, the routing could be done
more efficiently. The downside is that this pattern has a slightly worse matching
between the transistors and probably will have a worse immunity to temperature
gradients that the one used previously.
6.2.3 Output Stage
For the output stage, the six transistors were placed in an interdigitated manner,
similar to the one use in the current mirrors. The chosen pattern was ABABAB.
Again, this pattern was used to improve the matching between the transistors with
low compromise with the area.
41
6.3 Final Layout
The final layout with both blocks plugged together is shown at Figure 6.7. The
total area of this block is 138.24 µm x 104.295 µm. Note that this layout does not
have a guard ring around it.
Figure 6.7: Final layout of the buffer with descriptions of each block.
The external connections were placed in the sides of the die (east-west). The
layout has two ”holes” inside it, this unused area can still be used for placing some
capacitors for power supply decoupling.
42
Chapter 7
Post-layout simulation
After finishing the layout, we generated the extracted view, that takes into ac-
count resistive and capacitive parasitic effects of the layout. It’s important to use
this view because we can check how the layout has degraded the performance and
characteristics of the system with respect to the schematic view.
With this view, we could apply the same test bench, with the same test condi-
tions to this view and compare how the buffer behaves considering the resistive and
capacitive parasitic effects.
By using the extracted view, the obtained results are closer to the real world
application, so this step is mandatory if we want to proceed with this project.
7.1 Simulation Results
For all those simulations, we used the same test bench that was presented in
Chapter 5, as well as the same test conditions. This section will focus on showing
the results as the methodology was already previously explained.
7.1.1 Gain x Vid
The gain curve is shown in Figure 7.1 and its derivative in Figure 7.2. The results
were roughly the same as the schematic simulation. The slope with 1 VPP is 0.999
and with 1.2 VPP is 0.9967. This difference compared to to the schematic results is
43
negligible.
Vin diff Vout diff
V (
mV
)
-1000
-900.0
-800.0
-700.0
-600.0
-500.0
-400.0
-300.0
-200.0
-100.0
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000Name Vis
Vdc (m)-900.0 -700.0 -500.0 -300.0 -100.0 100.0 300.0 500.0 700.0 900.0
Vin diff:Vout diff Sat Aug 11 23:57:30 20181
Figure 7.1: Output differential voltage of a DC sweep simulation using the
extracted view.
gm
0.6
0.62
0.64
0.66
0.68
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1.0
1.02Name Vis
Vdc (m)-900.0 -700.0 -500.0 -300.0 -100.0 100.0 300.0 500.0 700.0 900.0
gm Sat Aug 11 23:57:30 20182
Figure 7.2: Derivative of the output differential voltage in a DC sweep
simulation using the extracted view.
44
7.1.2 AC Analysis
The results of the AC sweep simulation with the extracted view from the layout
are shown in Figure 7.3.
M2: 60.57189MHz -3.0dB phase gain (dB)
V (
deg)
-360.0
-340.0
-320.0
-300.0
-280.0
-260.0
-240.0
-220.0
-200.0
-180.0
-160.0
-140.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
20.0
(dB
)
-65.0
-60.0
-55.0
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0Name Vis
freq (Hz)10
-210
-110
010
110
210
310
410
510
610
710
810
910
10
phase:gain (dB) Sun Aug 12 00:19:20 20181
Figure 7.3: Output of an AC sweep in the buffer using the extracted view.
For comparison, the same three points that were shown in Chapter 5 are shown in
Table 7.1. The results are nearly the same as before. This shows that the parasitic
capacitances of the layout had little to no effect in the frequency response of the
buffer.
Frequency Gain Phase
300 kHz -1.3 mdB -0.4
3 MHz -1.7 mdB -3.9
30 MHz -307 mdB -42.1
Table 7.1: Results of three points in the AC sweep analysis using the extracted view.
45
7.1.3 Transient Analysis
We repeated the stability experiment that was described in Chapter 5. The results
are shown in Figure 7.4. We can see that the circuit did not lost its stability and
the common-mode feedback circuit can still sustain perturbations.
/Vinp /Vinn /Vout+ /Vout- /Vref
V (
V)
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1.0
1.05
1.1Name Vis
time (ms)0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
Transient Response Sun Aug 12 00:32:47 20182
Figure 7.4: Results from the stability test in the transient analysis using
extracted view.
7.1.4 THD
Figure 7.5 shows the result of the same parametric sweep test that was done
in Chapter 5. This test has not shown a significant difference compared to the
schematic simulation.
The results of the THD simulation are shown in Table 7.2. We also had a unim-
portant difference with respect to the schematic results.
46
thd
(m
)
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0
600.0
650.0
700.0
750.0
800.0Name Vis
Vac (m)380.0 400.0 420.0 440.0 460.0 480.0 500.0 520.0 540.0 560.0 580.0 600.0 620.0 640.0 660.0 680.0 700.0 720.0 740.0 760.0 780.0 800.0
thd Tue Sep 11 11:40:19 20181
Figure 7.5: Parametric sweep of the THD (in percentage), from 400 mV to
800 mV
Temperature Mean σ
-40 C 0.15% 0.07%
27 C 0.08% 0.04%
175 C 0.07% 0.03%
Table 7.2: Results from the 3 differents corners in the Monte Carlo Simulation for
the THD
7.1.5 Gain and Phase
The results from the Monte Carlo simulation with gain and phase are shown in
Table 7.3. From this results we can see that the difference between the schematic
view and the extracted view is negligible.
TemperatureMean
(Gain)
σ
(Gain)Mean (Phase) σ (Phase)
-40 C 0.999 0.007 -4.6 0.1
27 C 0.999 0.006 -5.3 0.2
175 C 1.000 0.005 -6.5 0.2
Table 7.3: Results from the 3 different corners in the Monte Carlo Simulation for
the gain and phase using the post layout extracted view.
47
78.4976m
μ
42.4214m
-σ
114.574m
σ
6.34515m
-2σ
150.650m
2σ
-29.7311m
-3σ
186.726m
3σ
thd
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
Values (m)-30.0 -10.0 10.0 30.0 50.0 70.0 90.0 110.0 130.0 150.0 170.0 190.0 210.0 220.0
Number = 100Mean = 78.4976mStd Dev = 36.0762m
thd 1
Figure 7.6: Histogram of the Monte Carlo simulation of the THD at typical
temperature using the extracted view.
145.617m
μ
74.3621m
-σ
216.872m
σ
3.10723m
-2σ
288.127m
2σ
-68.1476m
-3σ
359.382m
3σ
thd_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
Values (m)-100.0 -50.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0
Number = 100Mean = 145.617mStd Dev = 71.2549m
thd_t min 1
(a) Minimum Temperature (-40 C)
66.8981m
μ
37.0952m
-σ
96.7011m
σ
7.29219m
-2σ
126.504m
2σ
-22.5108m
-3σ
156.307m
3σ
thd_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Values (m)-30.0 -10.0 10.0 30.0 50.0 70.0 90.0 110.0 130.0 150.0 170.0 190.0
Number = 100Mean = 66.8981mStd Dev = 29.8030m
thd_t max 1
(b) Maximum Temperature (175 C)
Figure 7.7: Histogram of the Monte Carlo simulation of the THD at minimum (left) and
maximum (right) temperatures.
48
999.889m
μ
993.551m
-σ
1.00623
σ
987.213m
-2σ
1.01256
2σ
980.875m
-3σ
1.01890
3σ
gain
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
Values0.974 0.978 0.982 0.986 0.99 0.994 0.998 1.002 1.006 1.01 1.014 1.018 1.022 1.024
Number = 100Mean = 999.889mStd Dev = 6.33794m
gain 1
Figure 7.8: Histogram of the Monte Carlo simulation of the Gain at typical
temperature.
999.728m
μ
992.500m
-σ
1.00696
σ
985.271m
-2σ
1.01419
2σ
978.042m
-3σ
1.02141
3σ
gain_t min
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
Values0.97 0.975 0.98 0.985 0.99 0.995 1.0 1.005 1.01 1.015 1.02 1.025 1.03
Number = 100Mean = 999.728mStd Dev = 7.22872m
gain_t min 1
(a) Minimum Temperature (-40 C)
1.00041
μ
995.173m
-σ
1.00564
σ
989.938m
-2σ
1.01088
2σ
984.703m
-3σ
1.01611
3σ
gain_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
Values0.98 0.984 0.988 0.992 0.996 1.0 1.004 1.008 1.012 1.016 1.02
Number = 100Mean = 1.00041Std Dev = 5.23493m
gain_t max 1
(b) Maximum Temperature (175 C)
Figure 7.9: Histogram of the Gain at minimum (left) and maximum (right) temperatures.
49
-5.27660
μ
-5.44982
-σ
-5.10338
σ
-5.62304
-2σ
-4.93016
2σ
-5.79626
-3σ
-4.75695
3σ
phase
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
Values-5.9 -5.8 -5.7 -5.6 -5.5 -5.4 -5.3 -5.2 -5.1 -5.0 -4.9 -4.8 -4.7
Number = 100Mean = -5.27660Std Dev = 173.218m
phase 1
Figure 7.10: Histogram of the Monte Carlo simulation of the phase at typical
temperature.
-4.60564
μ
-4.75273
-σ
-4.45855
σ
-4.89983
-2σ
-4.31146
2σ
-5.04692
-3σ
-4.16436
3σ
phase_t min
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
Values-5.15 -5.1 -5.05 -5.0 -4.95 -4.9 -4.85 -4.8 -4.75 -4.7 -4.65 -4.6 -4.55 -4.5 -4.45 -4.4 -4.35 -4.3 -4.25 -4.2 -4.15 -4.1
Number = 100Mean = -4.60564Std Dev = 147.093m
phase_t min 1
(a) Minimum Temperature (-40 C)
-6.54327
μ
-6.80002
-σ
-6.28653
σ
-7.05676
-2σ
-6.02978
2σ
-7.31351
-3σ
-5.77304
3σ
phase_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Values-7.4 -7.3 -7.2 -7.1 -7.0 -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 -6.2 -6.1 -6.0 -5.9 -5.8 -5.7 -5.6
Number = 100Mean = -6.54327Std Dev = 256.744m
phase_t max 1
(b) Maximum Temperature (175 C)
Figure 7.11: Histogram of the Monte Carlo simulation of the phase at minimum (top)
and maximum (bottom) temperatures.
50
7.1.6 Input-Referred Noise
The results of the input-referred noise in the three temperatures are shown in
Table 7.4. The histograms are shown in figures 7.12, 7.13a and 7.13b. Those results
were slightly better than the simulation with the schematic. This is due the the
excess of parasitic capacitances of the extracted view, that act as a low-pass filter
for the noise.
Temperature Mean σ
-40 C 292.5 µV 4.4 µV
27 C 340.3 µV 5.6 µV
175 C 416.9 µV 7.4 µV
Table 7.4: Input-Referred Noise on three different temperatures.
340.318u
μ
334.733u
-σ
345.903u
σ
329.148u
-2σ
351.488u
2σ
323.563u
-3σ
357.073u
3σ
Band noise
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Values (u)320.0 322.0 324.0 326.0 328.0 330.0 332.0 334.0 336.0 338.0 340.0 342.0 344.0 346.0 348.0 350.0 352.0 354.0 356.0 358.0 360.0
Number = 100Mean = 340.318uStd Dev = 5.58505u
Band noise 1
Figure 7.12: Histogram of the Monte Carlo simulation of the Input-Referred
Noise at typical temperature.
51
292.486u
μ
288.128u
-σ
296.844u
σ
283.770u
-2σ
301.202u
2σ
279.412u
-3σ
305.560u
3σ
Band noise_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
Values (u)276.0 278.0 280.0 282.0 284.0 286.0 288.0 290.0 292.0 294.0 296.0 298.0 300.0 302.0 304.0 306.0 308.0 310.0
Number = 100Mean = 292.486uStd Dev = 4.35804u
Band noise_t min 1
(a) Minimum Temperature (-40 C)
416.919u
μ
409.464u
-σ
424.375u
σ
402.009u
-2σ
431.830u
2σ
394.553u
-3σ
439.285u
3σ
Band noise_t max
No.
of S
ampl
es
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
17
18
19
20
Values (u)390.0 395.0 400.0 405.0 410.0 415.0 420.0 425.0 430.0 435.0 440.0 445.0
Number = 100Mean = 416.919uStd Dev = 7.45536u
Band noise_t max 1
(b) Maximum Temperature (175 C)
Figure 7.13: Histogram of the Monte Carlo simulation of the Input-Referred Noise at
minimum (top) and maximum (bottom) temperatures.
7.1.7 Common-Mode Output Voltage
The results are shown in Table 7.5 and the histograms in Figures 7.14, 7.15a and
7.15b.
We can conclude that the physical implementation of the common-mode feedback
circuit has not caused a significant degradation in performance, as the common-
mode voltage kept close to the reference of 700 mV.
Temperature Mean σ
-40 C 696.1 mV 4.0 mV
27 C 695.7 mV 3.9 mV
175 C 694.0 mV 3.8 mV
Table 7.5: Common-Mode Output Voltage for three different temperatures.
The results of the output disparity are shown in Table 7.6 and the histograms in
Figures 7.16, 7.17a and 7.17b
Here we can see that, comparing the schematic results, the addition of parasitic
resistances in the post-layout simulation did not increased the output disparity.
52
695.766m
μ
691.811m
-σ
699.721m
σ
687.855m
-2σ
703.677m
2σ
683.900m
-3σ
707.632m
3σ
Common Mode
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
Values (m)678.0 680.0 682.0 684.0 686.0 688.0 690.0 692.0 694.0 696.0 698.0 700.0 702.0 704.0 706.0 708.0 710.0 712.0
Number = 100Mean = 695.766mStd Dev = 3.95536m
Common Mode 1
Figure 7.14: Histogram of the Monte Carlo simulation of the Common-Mode
Output Voltage at typical temperature.
696.150m
μ
692.105m
-σ
700.196m
σ
688.060m
-2σ
704.241m
2σ
684.015m
-3σ
708.286m
3σ
Common Mode_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (m)678.0 680.0 682.0 684.0 686.0 688.0 690.0 692.0 694.0 696.0 698.0 700.0 702.0 704.0 706.0 708.0 710.0 712.0
Number = 100Mean = 696.150mStd Dev = 4.04511m
Common Mode_t min 1
(a) Minimum Temperature (-40 C)
694.033m
μ
690.157m
-σ
697.910m
σ
686.280m
-2σ
701.786m
2σ
682.404m
-3σ
705.663m
3σ
Common Mode_t max
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (m)676.0 678.0 680.0 682.0 684.0 686.0 688.0 690.0 692.0 694.0 696.0 698.0 700.0 702.0 704.0 706.0 708.0 710.0
Number = 100Mean = 694.033mStd Dev = 3.87649m
Common Mode_t max 1
(b) Maximum Temperature (175 C)
Figure 7.15: Histogram of the Monte Carlo simulation of the Common-Mode Output
Voltage at minimum (left) and maximum (right) temperatures.
Temperature Mean σ
-40 C 2.3 mV 1.8 mV
27 C 2.2 mV 1.7 mV
175 C 2.1 mV 1.6 mV
Table 7.6: Output Disparity for three different temperatures.
53
2.20452m
μ
468.138u
-σ
3.94090m
σ
-1.26824m
-2σ
5.67728m
2σ
-3.00463m
-3σ
7.41367m
3σ
output disparity N
o. o
f Sam
ples
0.0
2.0
4.0
6.0
8.0
10
12
14
16
18
20
22
24
25
Values (m)-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9
Number = 100Mean = 2.20452mStd Dev = 1.73638m
output disparity 1
Figure 7.16: Histogram of the Monte Carlo simulation of the Output Dispar-
ity at typical temperature.
2.30597m
μ
500.392u
-σ
4.11154m
σ
-1.30518m
-2σ
5.91712m
2σ
-3.11076m
-3σ
7.72269m
3σ
output disparity_t min
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (m)-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
Number = 100Mean = 2.30597mStd Dev = 1.80557m
output disparity_t min 1
(a) Minimum Temperature (-40 C)
2.05997m
μ
421.619u
-σ
3.69833m
σ
-1.21673m
-2σ
5.33668m
2σ
-2.85509m
-3σ
6.97503m
3σ
output disparity_t max
No.
of S
ampl
es
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
Values (m)-3 -2 -1 0 1 2 3 4 5 6 7 8 9
Number = 100Mean = 2.05997mStd Dev = 1.63835m
output disparity_t max 1
(b) Maximum Temperature (175 C)
Figure 7.17: Histogram of the Monte Carlo simulation of the Output Disparity at mini-
mum (left) and maximum (right) temperatures.
54
Chapter 8
Conclusion
8.1 Analysis of the results
Our results had shown that this design is able to sustain the desired gain in
a high temperature range. In Figure 8.1 we can see five different curves of the
gain vs differential input, each one representing one temperature from the range
between −40 C to 175 C. Considering the region from −600 mV to 600 mV we
can se that there is a small variation in the behavior. Our results have shown that
even considering parasitic effects (from using the post-layout extraction) and process
mismatch effects (from the Monte Carlo simulations), the buffer kept the gain and
phase, for the target frequency of 3 MHz.
Figure 8.1: Gain vs differential input in five different temperatures.
55
We can also conclude that the techniques used in the layout phase have not
created a great disturbance in the buffer, comparing to the schematic results. When
contrasting both results, we se a very small difference in the performance, and for
some parameters, the results from the post-layout simulations were even better than
those considering only the schematic.
Considering the worst case of the THD, of 0.15% at −40 C, the SNR given by
the THD is equal to:
SNRTHD = 20 log( 1
0.0015
)= 56.5dB (8.1)
Our worst result with the noise bandwidth was with the maximum temperature
(175 C), is 416.9 mV. With this value, the SNR caused by the thermal noise is:
PM =V 2p
2=
0.62
2= 180 mW (8.2)
Pnoise = V 2noise = (416.9 m)2 = 173.8 nW (8.3)
SNRnoise = 10 log( PM
Pnoise
)= 10 log
( 180 mW
173.8 nW
)= 60.2 dB (8.4)
As the SNR given by the THD is lower than the one given by the thermal noise,
it will overlap the distortion created by the noise and will be the main limitation for
the resolution. If we want to use this buffer to sample an analog signal and them
convert it to digital, is important to take into account this distortion to determine
the maximum resolution of bits that is possible to achieve with this buffer. This
resolution can be calculated by comparing it with the ideal A/D converter, and is
given by the following equation:
SNR = 6.02 dB×N + 1.76 dB (8.5)
Where N is the number of bits and the constant 1.76 dB represents the
quantization noise, by plugging the value of our lowest SNR we have:
N =56.5− 1.76
6.02= 9.1 ≈ 9 bits (8.6)
56
This means that this buffer can be used for instrumentation applications where
the resolution is at maximum 9 bits.
A recapitulation of the performance is shown at Table 8.1. Those results show
that we successfully achieved our objective of designing a low power buffer with a
wide temperature range.
Parameter Value
Bit resolution 9
ω3dB 60 MHz
Capacitive load 15 pF
Output peak-to-peak 1.2 V
Operating Temperature −40 C to 175 C
Supply Voltage 1.8 V
Power Consumption 1.6 mW
Size 138.24 µm x 104.295 µm.
Table 8.1: Summary of the results.
8.2 Future Work
The next phase of this work would be the implementation in silicon of a prototype
for validating the design. With this prototype, we can perform some tests that could
not be performed by our CAD tools, such as applying temperature gradients.
We could also make more simulations for getting a better characterization of this
cell. Some common amplifier parameters include: Noise figure; Voltage and current
offset; Input impedance and others.
If the prototype is validated, this cell can be integrated into more complex systems
and could provide a low cost solution for interfacing internal signals from chips used
in embedded systems that work in high temperature variations.
57
Bibliography
[1] FERREIRA, P. M., BARUQUI, F. A., PETRAGLIA, A., “A 0.35 µm Cmos Am
demodulator”, Analog Integrated Circuits and Signal Processing, v. 57, n. 1-2,
pp. 89–96, 2008.
[2] “Apostila Microeletronica Graduacao”, http://www.pads.ufrj.br/ fbaruqui /Ar-
quivos/Apostila Micro.pdf, Accessed : 2018-08-08.
[3] SACKINGER, E., GUGGENBUHL, W., “A versatile building block: the CMOS
differential difference amplifier”, IEEE Journal of Solid-State Circuits, v. 22, n. 2,
pp. 287–294, 1987.
[4] KARKI, J., “Fully-differential amplifiers”, Application Report sloa054, , 2002.
[5] INSTRUMENTS, T., “Noise analysis in operational amplifier circuits”, Appli-
cation Report, SLVA043B, , 2007.
58
Appendix A - MOSFET Level 3 Model – XFAB XH018
Transistor NMOS-NEL
2
2
, :2 1
, :021
pGS T DS DSsat
GS T
Dp
GS T DS DS DS DSsat
GS T
k WV V saturation V V
L V VI
k WV V V V triode V V
L V V
0
1.72
0Tp pk k T T
0
300.74 10
TT TV V T T Vgs
Vsb
Vds
Id
0
12 SBV
0 0 0T T SBV V V GS TDSsat
V VV
NEL W = 1µm e L = 1µm SATURATION TRIODE MATCHING
0 0.39TV V 0 1.23SBV
0 0.48TV V 0 1.23SBV
2 2 1827 10pk pk WL
2293.4pk A V 0.25 2293.4pk A V 0.34
0
2 2 180 82 10
TV TV WL
0 0.58V 0.48 0 0.58V 0.48 3 28.6 10oxC F m
NEL W = 1µm e L = 0.5µm SATURATION TRIODE MATCHING
0 0.39TV V 0 1.24SBV
0 0.5TV V 0 1.24SBV
2 2 1827 10pk pk WL
2292.6pk A V 0.78 2292.6pk A V 0.39
0
2 2 180 82 10
TV TV WL
0 0.51V 0.46 0 0.51V 0.46 3 28.6 10oxC F m
NEL W = 1µm e L = 0.18µm SATURATION TRIODE MATCHING
0 0.3TV V 0 1.24SBV
0 0.47TV V 0 1.24SBV
2 2 1827 10pk pk WL
2360.5pk A V 1.42 2360.5pk A V 0.74
0
2 2 180 138.6 10
TV TV WL
0 0.4V 0.33 0 0.4V 0.33 3 28.6 10oxC F m
NEL W = 5µm e L = 5µm SATURATION TRIODE MATCHING
0 0.4TV V 0 1.24SBV
0 0.48TV V 0 1.24SBV
2 2 1827 10pk pk WL
2333.1pk A V 0.38 2333.1pk A V 0.31
0
2 2 180 86.3 10
TV TV WL
0 0.31V 0.35 0 0.31V 0.35 3 28.6 10oxC F m
Transistor PMOS-PEL
2
2
, :2 1
, :021
pSG T SD SDsat
SG T
Dp
SG T SD SD SD SDsat
SG T
k WV V saturation V V
L V VI
k WV V V V triode V V
L V V
0
1.2
0Tp pk k T T
0
300.88 10
TT TV V T T
12 2 BSV
0 2 2T T BSV V V SG TSDsat
V VV
PEL W = 1µm e L = 1µm SATURATION TRIODE MATCHING
0 0.38TV V 0 1.21SBV
0 0.47TV V 0 1.21SBV
2 2 1842 10pk pk WL
274.4pk A V 0.28 274.4pk A V 0.32
0
2 2 180 84 10
TV TV WL
0 0.71V 0.43 0 0.71V 0.43 3 29.1 10oxC F m
PEL W = 1µm e L = 0.5µm SATURATION TRIODE MATCHING
0 0.38TV V 0 1.2SBV
0 0.47TV V 0 1.2SBV
2 2 1842 10pk pk WL
280.7pk A V 0.35 280.7pk A V 0.43
0
2 2 180 84 10
TV TV WL
0 0.52V 0.39 0 0.52V 0.39 3 29.1 10oxC F m
PEL W = 1µm e L = 0.18µm SATURATION TRIODE MATCHING
0 0.34TV V 0 1.17SBV
0 0.46TV V 0 1.17SBV
2 2 1842 10pk pk WL
2124.1pk A V 0.85 2124.1pk A V 0.99
0
2 2 180 67 10
TV TV WL
0 0.48V 0.32 0 0.48V 0.32 3 29.1 10oxC F m
PEL W = 5µm e L = 5µm SATURATION TRIODE MATCHING
0 0.34TV V 0 1.22SBV
0 0.45TV V 0 1.22SBV
2 2 1842 10pk pk WL
278.8pk A V 0.31 278.8pk A V 0.34
0
2 2 180 67 10
TV TV WL
0 1.12V 0.54 0 1.12V 0.54 3 29.1 10oxC F m