Post on 19-Sep-2020
Microeletrônica
q Professor: Fernando Gehm Moraesq Livro texto:
Digital Integrated Circuits a Design Perspective - RabaeyC MOS VLSI Design - Weste
Revisão das lâminas: 22/setembro/2020
Aula #5 à Portas lógicas dinâmicas
Lógica Combinacional• Os sinais de saída de um circuito são resultados de
uma combinação lógica dos sinais de entrada atuais
Lógica Estática (portas CMOS)As saídas só mudam de valores a partir da mudança dos valores de entrada
Lógica DinâmicaAs saídas representam o resultado da combinação lógica durante um tempo pré-determinado
2
Dynamic CMOS• In static circuits at every point in time (except
when switching) the output is connected to either GND or VDD via a low resistance path.• fan-in of n requires 2n (n N-type + n P-type) devices
• Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.• requires on n + 2 (n+1 N-type + 1 P-type) transistors
3
Lógica Dinâmica Combinacional
Mp
Me
VDD
PDN
f
In1In2In3
OutMe
Mp
VDD
PUN
f
In1In2In3
f
f
Out
CL
CL
fp networkfn network
2 phase operation:• Evaluation
• PrechargeOperacão em 2 fases: pré-carga / avaliação O valor de saída da porta lógica
fica armazenado na capacitância de saída (próxima porta)
Dá-se preferência por PND è mais rápido 4
Dynamic Gate
5
In1In2 PDNIn3
Me
Mp
Clk
ClkOut
CL
Out
Clk
Clk
A
BC
Mp
Me
Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)
on
off
1off
on
((AB)+C)
Resposta a transientes
0.00e+00 2.00e-09 4.00e-09 6.00e-09t (nsec)
0.0
2.0
4.0
6.0Vo
ut (V
olt)
f Vout
PRECHARGEEVALUATION
6
Lógica CombinacionalPorta NAND Dinâmica de 4 Entradas
In1In2In3In4
Out
VDD
GNDf
7
Observação quanto às transições de entrada
• Once the output of a dynamic gate is discharged, it cannotbe charged again until the next precharge operation.
• Inputs to the gate can make at most one transition during evaluation.
8
Out
Clk
Clk
A
BC
q Por exemplo: no início da avaliação temos ABC=001, descarregando a saída (Out=0)
q Se C passar para 0 durante a avaliação, a saída não irá para 1
Observação quanto à saída• Output can be in the high impedance state during the
evaluation (PDN off), state is stored on CL
9
Out
Clk
Clk
A
BC
q Por exemplo: na pré-carga a saída é carregada com 1 (Out=1)
q Se na avaliação tivermos ABC=000 a saída fica em alta-impedância, mas mantém o 1 da pré-carga na capacitância de saída
Properties of Dynamic Gates• Logic function is implemented by the PDN only
• number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)• Faster switching speeds
• reduced load capacitance due to lower input capacitance (Cin)• reduced load capacitance due to smaller output loading (Cout)
Ou seja: (1) menores capacitâncias de entrada devido ao menor número
de transistores(2) o tempo de subida (mais lento) não existe, devido à pré-
carga10
Issues in Dynamic Design 1: Charge Leakage
11
CL
Clk
ClkOut
A
Mp
Me
Leakage sources
CLK
VOut
Precharge
Evaluate
O valor armazenado na saída tem “fuga”, devido ao fato que o gate não é completamente isolado
Solution to Charge Leakage
12
CL
Clk
Clk
Me
Mp
A
B
Out
Mkp
• O keeper é de fato um circuito de memória. • Se a saída da célula for 1 (situação de perda de sinal por leakege), a
saída do inversor é 0, fazendo o keeper conduzir, forçando um 1 na entrada do inversor.
Keeper
Issues in Dynamic Design 2: Charge Sharing
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CL
Clk
Clk
CA
CB
B=0
AOut
Mp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
Charge Sharing Example
14
CL=50fF
Clk
Clk
A A
B B B !B
CC
Out
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
Solution to Charge Redistribution
15
Clk
Clk
Me
Mp
A
B
OutMkp Clk
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
Como conectar portas dinâmicas
16
Clk
Clk
Out1In
Mp
Me
Mp
Me
Clk
Clk
Out2
V
t
Clk
In
Out1
Out2 DV
VTn
Only 0 ® 1 transitions allowed at inputs!
Dois inversores em cascata è espera-se que out2 seja igual a In• out1 demora um pouco para descer, e este pequeno tempo faz out2 começar a
descer também• No momento que out1 chegou a zero, out2 para de descer e fica em estado
indefinido
Transições de ‘1’ para ‘0’podem levar a estadosindeterminados na porta seguinte
Simulação
17
Pré-carga
Avaliação
o1 e o2 começam a descarregar juntos
1 ® 0 não pode pois NÃO tem pull-up
Lógica Dinâmica - Dominó
Mp
Me
VDD
PDN
f
In1In2In3
Out1
f
Mp
Me
VDD
PDN
f
In4
f
Out2
Mr
VDD
Static Inverterwith Level Restorer
1 ® 11 ® 0
0 ® 00 ® 1
O circuito é pré-carreado, e depois pode tanto fazer transição para ‘1’ quanto para ‘0’ – modo normal de lógica dinâmica
Na pré-carga, a saída do inversor é 0. Logo só haverá transição de subida (para descarga) 18
19
Clk
Clko3
In
Clk
Clk
o5
Simulação
o4 o6
Pré-carga
0 à 1Saída em 0
Avaliação
Saída em 0Saída correta (=Vin)
Características:
Lógica Dinâmica - Dominó
• Lógica não-invertida
• Muita rápida
• A adição de um regenerador de nível de sinal reduz as correntes de fuga e os problemas de distribuição de cargas
20
Solução alternativa: np-CMOS
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In1In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 ® 11 ® 0
0 ® 00 ® 1
Only 0 ® 1 transitions allowed at inputs of PDN Only 1 ® 0 transitions allowed at inputs of PUN
22
In1In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 ® 11 ® 0
0 ® 00 ® 1
to otherPDN’s
to otherPUN’s
Famílias CMOS (Weste – Cap 9)
23
Chapter 9 Combinational Circuit Design350
pass-transistor circuits are essentially equivalent ways to draw the fundamental logic struc-tures we have explored before. An independent evaluation finds that for most general-purpose logic, static CMOS is superior in speed, power, and area [Zimmermann97].
For the purpose of comparison, Figure 9.47 shows a 2-input multiplexer constructedin a wide variety of pass-transistor circuit families along with static CMOS, pseudo-nMOS, CVSL, and single- and dual-rail domino. Some of the circuit families are dual-rail, producing both true and complementary outputs, while others are single-rail and mayrequire an additional inversion if the other polarity of output is needed. U XOR V can be
Static CMOS
CMOSTG
CPL EEPL DCVSPG
SRPL
LEAP
Pseudo-nMOS CVSL
Domino Dual-Rail Domino
A
B
S
S
S
Y
SY
A B
S
S S
BA
Y
A B
SS S
B A
YS
BA
Y
A B
SS
!Y
! Y_hY_l
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
AY
Y
B
S
S
S
A
B
A
Y
Y
S
B
S
SA
Y
S
BS
S
S
A
B
A
PPL
A
B
S
S
S
Y
S
S
A
B
Y
DPL
HH H
L
L
L
L
L
L
SS
S
B A
S
BA
SS
Y
Y
Y
Y
Y
Y
L
FIGURE 9.47 Comparison of circuit families for 2-input multiplexers
Chapter 9 Combinational Circuit Design350
pass-transistor circuits are essentially equivalent ways to draw the fundamental logic struc-tures we have explored before. An independent evaluation finds that for most general-purpose logic, static CMOS is superior in speed, power, and area [Zimmermann97].
For the purpose of comparison, Figure 9.47 shows a 2-input multiplexer constructedin a wide variety of pass-transistor circuit families along with static CMOS, pseudo-nMOS, CVSL, and single- and dual-rail domino. Some of the circuit families are dual-rail, producing both true and complementary outputs, while others are single-rail and mayrequire an additional inversion if the other polarity of output is needed. U XOR V can be
Static CMOS
CMOSTG
CPL EEPL DCVSPG
SRPL
LEAP
Pseudo-nMOS CVSL
Domino Dual-Rail Domino
A
B
S
S
S
Y
SY
A B
S
S S
BA
Y
A B
SS S
B A
YS
BA
Y
A B
SS
!Y
! Y_hY_l
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
AY
Y
B
S
S
S
A
B
A
Y
Y
S
B
S
SA
Y
S
BS
S
S
A
B
A
PPL
A
B
S
S
S
Y
S
S
A
B
Y
DPL
HH H
L
L
L
L
L
L
SS
S
B A
S
BA
SS
Y
Y
Y
Y
Y
Y
L
FIGURE 9.47 Comparison of circuit families for 2-input multiplexers
CVSL - Cascode Voltage Switch Logic
10: Circuit Families24
CPLqComplementary Pass-transistor Logic
§ Dual-rail form of pass transistor logic§ Avoids need for ratioed feedback§ Optional cross-coupling for rail-to-rail swing
Chapter 9 Combinational Circuit Design350
pass-transistor circuits are essentially equivalent ways to draw the fundamental logic struc-tures we have explored before. An independent evaluation finds that for most general-purpose logic, static CMOS is superior in speed, power, and area [Zimmermann97].
For the purpose of comparison, Figure 9.47 shows a 2-input multiplexer constructedin a wide variety of pass-transistor circuit families along with static CMOS, pseudo-nMOS, CVSL, and single- and dual-rail domino. Some of the circuit families are dual-rail, producing both true and complementary outputs, while others are single-rail and mayrequire an additional inversion if the other polarity of output is needed. U XOR V can be
Static CMOS
CMOSTG
CPL EEPL DCVSPG
SRPL
LEAP
Pseudo-nMOS CVSL
Domino Dual-Rail Domino
A
B
S
S
S
Y
SY
A B
S
S S
BA
Y
A B
SS S
B A
YS
BA
Y
A B
SS
!Y
! Y_hY_l
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
AY
Y
B
S
S
S
A
B
A
Y
Y
S
B
S
SA
Y
S
BS
S
S
A
B
A
PPL
A
B
S
S
S
Y
S
S
A
B
Y
DPL
HH H
L
L
L
L
L
L
SS
S
B A
S
BA
SS
Y
Y
Y
Y
Y
Y
L
FIGURE 9.47 Comparison of circuit families for 2-input multiplexers
Alternative CPL
25
9.2 Circuit Families 353
include the inverters from the previous stage that drives the diffusion input, but to excludethe output inverters. Figure 9.53(c) shows the mux drawn at the transistor level. Observethat this is identical to the CVSL gate from Figure 9.47 except that the internal node ofthe stack can be pulled up through the weak pMOS transistors in the inverters.
When the gate switches, one side pulls down well through its nMOS transistors. Theother side pulls up. CPL can be constructed without cross-coupled pMOS transistors, butthe outputs would only rise to VDD – Vt (or slightly lower because the nMOS transistorsexperience the body effect). This costs static power because the output inverter will beturned slightly ON. Adding weak cross-coupled devices helps bring the rising output tothe supply rail while only slightly slowing the falling output. The output inverters can beLO-skewed to reduce sensitivity to the slowly rising output.
9.2.5.3 Lean Integration with Pass Transistors (LEAP) Like CPL, LEAP6 [Yano96]builds logic networks using only fast nMOS transistors, as shown in Figure 9.47. It is asingle-ended logic family in that the complementary network is not required, thus savingarea and power. The output is buffered with an inverter, which can be LO-skewed to favorthe asymmetric response of an nMOS transistor. The nMOS network only pulls up toVDD – Vt so a pMOS feedback transistor is necessary to pull the internal node fully high,avoiding power consumption in the output inverter. The pMOS width is a trade-offbetween fighting falling transitions and assisting the last part of a rising transition; it gen-erally should be quite weak and the circuit will fail if it is too strong. LEAP can be a goodway to build wide 1-of-N hot multiplexers with many of the advantages of pseudo-nMOSbut without the static power consumption. It was originally proposed for use in a passtransistor logic synthesis system because the cells are compact.
Unlike most circuit families that can operate down to VDD v max(Vtn, |Vtp|), LEAP islimited to operating at VDD v 2Vt because the inverter must flip even when receiving aninput degraded by a threshold voltage.
9.2.5.4 Other Pass Transistor Families There have been a host of pass transistor familiesproposed in the literature, including Differential Pass Transistor Logic (DPTL)[Pasternak87, Pasternak91], Double Pass Transistor Logic (DPL) [Suzuki93], Energy Econ-omized Pass Transistor Logic (EEPL) [Song96], Push-Pull Pass Transistor Logic (PPL)[Paik96], Swing-Restored Pass Transistor Logic (SRPL) [Parameswar96], and DifferentialCascode Voltage Switch with Pass Gate Logic (DCVSPG) [Lai97]. All of these are dual-railfamilies like CPL, as contrasted with the single-rail CMOSTG and LEAP.
6The LEAP topology was reinvented under the name Single Ended Swing Restoring Pass Transistor Logic[Pihl98].
S
BA
Y
S
B A
Y
SS
S
B A
S
BA
SSL L
(a) (c)
S
B A
YS
BA
YSS
L L L L
Y Y
(b)
FIGURE 9.53 Alternate representations of CPL
26
LEAPqLEAn integration with Pass transistorsq Get rid of pMOS transistors
§ Use weak pMOS feedback to pull fully high§ Ratio constraint
Chapter 9 Combinational Circuit Design350
pass-transistor circuits are essentially equivalent ways to draw the fundamental logic struc-tures we have explored before. An independent evaluation finds that for most general-purpose logic, static CMOS is superior in speed, power, and area [Zimmermann97].
For the purpose of comparison, Figure 9.47 shows a 2-input multiplexer constructedin a wide variety of pass-transistor circuit families along with static CMOS, pseudo-nMOS, CVSL, and single- and dual-rail domino. Some of the circuit families are dual-rail, producing both true and complementary outputs, while others are single-rail and mayrequire an additional inversion if the other polarity of output is needed. U XOR V can be
Static CMOS
CMOSTG
CPL EEPL DCVSPG
SRPL
LEAP
Pseudo-nMOS CVSL
Domino Dual-Rail Domino
A
B
S
S
S
Y
SY
A B
S
S S
BA
Y
A B
SS S
B A
YS
BA
Y
A B
SS
!Y
! Y_hY_l
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
A
B
S
S
S
S
A
B
AY
Y
B
S
S
S
A
B
A
Y
Y
S
B
S
SA
Y
S
BS
S
S
A
B
A
PPL
A
B
S
S
S
Y
S
S
A
B
Y
DPL
HH H
L
L
L
L
L
L
SS
S
B A
S
BA
SS
Y
Y
Y
Y
Y
Y
L
FIGURE 9.47 Comparison of circuit families for 2-input multiplexers
Outras Famílias com TGs
27
• DPTL (Differential Pass Transistor Logic)
• DPL (Double Pass Transistor Logic)
• EEPL (Energy Economized Pass Transistor Logic)
• PPL (Push-Pull Pass Transistor Logic)
• SRPL (Swing Restored Pass Transistor Logic)
• DCVSPG (Differential Cascode Voltage Switch
with Pass Gate Logic