Post on 05-Jan-2016
description
MC542 3.1
2007
Prof. Paulo Cesar Centoducatte
ducatte@ic.unicamp.br
www.ic.unicamp.br/~ducatte
MC542
Organização de ComputadoresTeoria e Prática
MC542 3.2
MC542
Arquitetura de Computadores
Micro-Arquitetura
“DDCA” - (Capítulo 7)
“COD” - (Capítulo)
MC542 3.3
Micro-Arquitetura
• Micro-Arquitetura– Introdução– Recursos– MIPS Mono-Ciclo
» Lw» Sw» R-Type» Beq» j
– MIPS Múlti-Ciclos» Lw» Sw» R-Type» Beq» j
MC542 3.4
Introdução
• Micro-arquitetura: como está implementada a arquitetura em hardware
• Processador:– Datapath: blocos funcionais– Controle: sinais de controle
Physics
Devices
Analog
Circuits
Digital
Circuits
Logic
Micro-
architecture
Architecture
Operating
Systems
Application
Software
electrons
transistors
diodes
amplifiers
filters
AND gates
NOT gates
adders
memories
datapaths
controllers
instructions
registers
device drivers
programs
MC542 3.5
Micro-Arquitetura
• Múltiplas implementações para uma mesma arquitetura:
– Single-cycle» Cada instrução é executada em um único ciclo
– Multicycle» A execução de cada instrução é dividida em uma
série de passos menores
– Pipelined» A execução de cada instrução é dividida em uma
série de passos menores » Múltiplas instruções (parte de) executando ao
mesmo tempo.
MC542 3.6
Micro-Arquitetura
• Program execution time
Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)
• Definições:– Cycles/instruction = CPI– Seconds/cycle = clock period– 1/CPI = Instructions/cycle = IPC
• Desafios na implementação de uma micro-arquitetura
– Custo– Power– Desempenho
MC542 3.7
Micro-Arquitetura
• Processador MIPS (Microprocessor without Interlolocked Pipeline Stages)
– Vamos implementar um sub conjunto das instruções MIPS:
– R-type instructions: and, or, add, sub, slt– Memory instructions: lw, sw– Branch instructions: beq
MC542 3.8
Micro-Arquitetura
• Estado da Arquitetura
– Determina o estado do Processador em um dado instante de tempo
PC
32 registradoresMemória
MC542 3.9
Micro-Arquitetura
• Elementos de estados do MIPS:
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
Data
Memory
WD
WE
PCPC'
CLK
32 32
32 32
32
32
32
32
32
32
5
5
5
MC542 3.10
Processador MIPS Single-Cycle
• Datapath
• Controle
MC542 3.11
Processador MIPS Single-Cycle
• Execução de lw
1: Fetch da Instrução
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
Instr
CLK
MC542 3.12
Processador MIPS Single-Cycle
• Execução de lw
2: Lê o operando fonte do RF
Instr
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
25:21
CLK
MC542 3.13
Processador MIPS Single-Cycle
• Execução de lw
3: Sign-extend o imediato
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
CLK
MC542 3.14
Processador MIPS Single-Cycle
• Execução de lw
4: Calcula o endereço efetivo de memória
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA Zero
CLK
ALUControl2:0
ALU
010
MC542 3.15
Processador MIPS Single-Cycle
• Execução de lw
5: Lê o dado da memória e o escreva no RF
A1
A3
WD3
RD2
RD1WE3
A2
SignImm
CLK
A RD
InstructionMemory
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
MC542 3.16
Processador MIPS Single-Cycle
• Execução de lw
6: Determina o endereço da próxima instrução
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
PCPlus4
Result
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
MC542 3.17
Processador MIPS Single-Cycle
• Execução de sw• Precisa escrever o valor do registrador na
memória
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
20:16
15:0
SrcB20:16
ALUResult ReadData
WriteData
SrcA
PCPlus4
Result
MemWriteRegWrite
Zero
CLK
ALUControl2:0
ALU
10100
MC542 3.18
Processador MIPS Single-Cycle
• Instruções R-Type: add, sub, and, or, ….• Escrever ALUResult no RF
– Escreve em rd e não em rt
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PCPC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
ALUResult ReadData
WriteData
SrcA
PCPlus4WriteReg4:0
Result
RegDst MemWrite MemtoRegALUSrcRegWrite
Zero
CLK
ALUControl2:0
ALU
0varies1 001
MC542 3.19
Processador MIPS Single-Cycle• Instrução beq• Determina se os conteúdos dos registradores
são iguais• Calcula o endereço alvo do desvio (sign-
extended immediate + PC+4)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1
PC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
RegDst Branch MemWrite MemtoRegALUSrcRegWrite
Zero
PCSrc
CLK
ALUControl2:0
ALU
01100 x0x 1
MC542 3.20
Processador MIPS Single-Cycle - or
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0010
01
0
0
1
0
MC542 3.21
Processador MIPS Single-Cycle - sw
ImmExt
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC
0
1
PC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
RegDst Branch MemWrite MemtoRegALUSrcRegWrite
ZeroPCSrc
CLK
ALUControl2:0
AL
U
MC542 3.22
Processador MIPS Single-Cycle
• Unidade de Controle
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
MC542 3.23
Processador MIPS Single-Cycle
RegDst
Branch
MemWrite
MemtoReg
ALUSrcOpcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainDecoder
ALUOp1:0
ALUDecoder
RegWrite
Control Unit
MC542 3.24
Processador MIPS Single-Cycle
• ALU
F2:0Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
ALU
N N
N
3
A B
Y
F
MC542 3.25
Processador MIPS Single-Cycle
• ALU
+
2 01
A B
Cout
Y3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
roE
xtend
MC542 3.26
Processador MIPS Single-Cycle
• ALU Decoder
ALUOp1:0 Meaning
00 Add
01 Subtract
10 Look at Funct
11 Not Used
ALUOp1:0Funct ALUControl2:0
00 X 010 (Add)
X1 X 110 (Subtract)
1X 100000 (add) 010 (Add)
1X 100010 (sub) 110 (Subtract)
1X 100100 (and) 000 (And)
1X 100101 (or) 001 (Or)
1X 101010 (slt) 111 (SLT)
MC542 3.27
Processador MIPS Single-Cycle
• Decodificador Principal
Instruction
Op5:0RegWrit
eRegD
stAluSr
cBranc
hMemWrit
eMemtoR
egALUOp1
:0
R-type 000000
1 1 0 0 0 0 10
lw 100011
1 0 1 0 0 0 00
sw 101011
0 X 1 0 1 X 00
beq 000100
0 X 0 1 0 X 01
MC542 3.28
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: addi
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
MC542 3.29
Processador MIPS Single-Cycle
• Decodificador Principal
Instruction Op5:0
RegWrite
RegDst
AluSrc
Branch
MemWrite
MemtoReg
ALUOp1:
0
R-type00000
0 1 1 0 0 0 0 10
lw10001
1 1 0 1 0 0 1 00
sw10101
1 0 X 1 0 1 X 00
beq00010
0 0 X 0 1 0 X 01
addi 001000 1 0 1 0 0 0 00
MC542 3.30
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: j
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
MC542 3.31
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: j
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542 3.32
Processador MIPS Single-Cycle
• Decodificador Principal
Instruction Op5:0
RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
Jump
R-type 000000 1 1 0 0 0 0 10 0
lw 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
addi 001000 1 0 1 0 0 0 00 0
j 000100 0 X X X 0 X XX 1
MC542 3.33
Processador MIPS Single-Cycle
• Desempenho: Quão rápido é o processador?
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542 3.34
Processador MIPS Single-Cycle
• O cycle time é limitado pelo caminho crítico: lw
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU1
0100
1
0
1
0 0
MC542 3.35
Processador MIPS Single-Cycle
• Caminho crítico
Tc = tpcq_PC + tmem + max(tRFread, tsext) + tmux + tALU + tmem + tmux + tRFsetup
• Na maioria das implementações os caminhos limitantes são: memória, ALU, register file. Assim,
Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup
MC542 3.36
Processador MIPS Single-Cycle
Element Parameter Delay (ps)
Register clock-to-Q
tpcq_PC30
Register setup tsetup20
Multiplexer tmux25
ALU tALU200
Memory read tmem250
Register file read tRFread150
Register file setup
tRFsetup20
Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup
= [30 + 2(250) + 150 + 2(25) + 200 + 20] ps = 950 ps
MC542 3.37
Processador MIPS Single-Cycle
• Para um programa 100 bilhões de instruções executando em um processador MIPS single-cycle,
Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)
= (100 × 109)(1)(950 × 10-12 s)
= 95 seconds
MC542 3.38
Processador MIPS Multicycle
• Datapath
• Controle
MC542 3.39
Processador MIPS Multicycle
• Blocos Básicos
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
PCPC'
WD
WE
CLK
EN
ALU
Restrição de Projeto:
Somente 1 bloco acima pode ser
usado por vez
MC542 3.40
Processador MIPS Multicycle
• Datapath– datapath para o lw
Exemplo: lw $s4, 27($t2)
• Fetch da Instrução
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
PCPC' Instr
CLK
WD
WE
CLK
EN
IRWrite
MC542 3.41
Processador MIPS Multicycle
• Leitura do operando fonte do RF (rs)
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
PCPC' Instr25:21
CLK
WD
WE
CLK CLK
A
EN
IRWrite
MC542 3.42
Processador MIPS Multicycle
• Sign-Extend o Imediato
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
PCPC' Instr25:21
15:0
CLK
WD
WE
CLK CLK
A
EN
IRWrite
MC542 3.43
Processador MIPS Multicycle
• Soma do Base Address ao Offset
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
PCPC' Instr25:21
15:0
SrcB
ALUResult
SrcA
ALUOut
CLK
ALUControl2:0
ALU
WD
WE
CLK CLK
A CLK
EN
IRWrite
MC542 3.44
Processador MIPS Multicycle
• Carga do dado a partir da Memória
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
PCPC' Instr25:21
15:0
SrcB
ALUResult
SrcA
ALUOut
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
Data
CLK
CLK
A CLK
EN
IRWriteIorD
0
1
MC542 3.45
Processador MIPS Multicycle
• Escrita do Dado no Register File
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
PCPC' Instr25:21
15:0
SrcB20:16
ALUResult
SrcA
ALUOut
RegWrite
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
Data
CLK
CLK
A CLK
EN
IRWriteIorD
0
1
MC542 3.46
Processador MIPS Multicycle
• Incremento do PC de 4
PCWrite
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1PCPC' Instr25:21
15:0
SrcB
20:16
ALUResult
SrcA
ALUOut
ALUSrcARegWrite
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
Data
CLK
CLK
A
00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorD
0
1
MC542 3.47
Processador MIPS Multicycle
• Datapath também para sw
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
ALUResult
SrcA
ALUOut
MemWrite ALUSrcARegWrite
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
Data
CLK
CLK
A
00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorDPCWrite
B
MC542 3.48
Processador MIPS Multicycle
• Datapath para instruções R-Type
0
1
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
15:11
ALUResult
SrcA
ALUOut
RegDstMemWrite MemtoReg ALUSrcARegWrite
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorDPCWrite
MC542 3.49
Processador MIPS Multicycle
• Datapath para beq
SignImm
b
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorD PCWrite
PCEn
MC542 3.50
Processador MIPS Multicycle
• Datapath para o Processador Multicycle
ImmExt
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorD PCWrite
PCEn
MC542 3.51
Processador MIPS Multicycle
• Controle para o Processador Multicycle
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC 0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
RegD
st
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
MC542 3.52
Processador MIPS Multicycle
• Unidade de controle
ALUSrcA
PCSrc
Branch
ALUSrcB1:0
Opcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainController
(FSM)
ALUOp1:0
ALUDecoder
RegWrite
PCWrite
IorD
MemWrite
IRWrite
RegDst
MemtoReg
RegisterEnables
MultiplexerSelects
MC542 3.53
Processador MIPS Multicycle
• Unidade de Controle– Finite State Machine– Diagrama de transição de estados para lw
MC542 3.54
Processador MIPS Multicycle
• Fetch da Instrução
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC 0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
Re
gDst
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
0
1 1
0
X
X
00
01
0100
1
0
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
Reset
S0: Fetch
MC542 3.55
Processador MIPS Multicycle
• Decodificação da Instrução
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
Reset
S0: Fetch S1: Decode
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC 0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
Re
gDst
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
X
0 0
0
X
X
0X
XX
XXXX
0
0
MC542 3.56
Processador MIPS Multicycle
• Cálculo do endereço efetivo
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
Reset
S0: Fetch
S2: MemAdr
S1: Decode
Op = LWor
Op = SW
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC 0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
Re
gDst
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
X
0 0
0
X
X
01
10
010X
0
0
MC542 3.57
Processador MIPS Multicycle
• Leitura da Memória e
Escrita no RF IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
Op = LWor
Op = SW
Op = LW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
MC542 3.58
Processador MIPS Multicycle
• Diagrama de transição de estados para sw
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1IorD = 1
MemWrite
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
Op = LWor
Op = SW
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
MC542 3.59
Processador MIPS Multicycle
• Diagrama de transição de estados para R-type
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1RegDst = 1
MemtoReg = 0RegWrite
IorD = 1MemWrite
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
S6: Execute
S7: ALUWriteback
Op = LWor
Op = SW
Op = R-type
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
MC542 3.60
Processador MIPS Multicycle
• Diagrama de transição de estados para beq
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1RegDst = 1
MemtoReg = 0RegWrite
IorD = 1MemWrite
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
S6: Execute
S7: ALUWriteback
S8: Branch
Op = LWor
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
MC542 3.61
Processador MIPS Multicycle
• FSM de ControleIorD = 0
AluSrcA = 0ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1RegDst = 1
MemtoReg = 0RegWrite
IorD = 1MemWrite
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
S6: Execute
S7: ALUWriteback
S8: Branch
Op = LWor
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
MC542 3.62
Processador MIPS Multicycle
• Extendendo a Funcionalidade para addi
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC 0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
RegD
st
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
MC542 3.63
Processador MIPS Multicycle
• FSM de Controle para addi
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 0
IRWritePCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1RegDst = 1
MemtoReg = 0RegWrite
IorD = 1MemWrite
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
S6: Execute
S7: ALUWriteback
S8: Branch
Op = LWor
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst = 0MemtoReg = 0
RegWrite
Op = ADDI
S9: ADDIExecute
S10: ADDIWriteback
MC542 3.64
Processador MIPS Multicycle
• Extendendo a Funcionalidade para j
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc1:0
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorD PCWrite
PCEn
00
01
10
<<2
25:0 (jump)
31:28
27:0
PCJump
MC542 3.65
Processador MIPS Multicycle
• FSM de Controle para j
IorD = 0AluSrcA = 0
ALUSrcB = 01ALUOp = 00PCSrc = 00
IRWritePCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
IorD = 1RegDst = 1
MemtoReg = 0RegWrite
IorD = 1MemWrite
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCSrc = 01
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemReadS5: MemWrite
S6: Execute
S7: ALUWriteback
S8: Branch
Op = LWor
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0MemtoReg = 1
RegWrite
S4: MemWriteback
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst = 0MemtoReg = 0
RegWrite
Op = ADDI
S9: ADDIExecute
S10: ADDIWriteback
PCSrc = 10PCWrite
Op = J
S11: Jump
MC542 3.66
Processador MIPS Multicycle
• Desempenho: Quão rápido é o processador?
• Instruções gastam números diferentes de ciclos:– 3 ciclos: beq, j– 4 ciclos: R-Type, sw, addi– 5 ciclos: lw
• O CPI deve ser a média ponderada• SPECINT2000 benchmark:
– 25% loads– 10% stores – 11% branches– 2% jumps– 52% R-type
Average CPI = (0.11 + 0.2)(3) + (0.52 + 0.10)(4) + (0.25)(5) = 4.12
MC542 3.67
Processador MIPS Multicycle
• Caminho Crítico
Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup
SignImm
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1 0
1
PC0
1
PC' Instr25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
Re
gD
st
Branch
MemWrite
Mem
toReg
ALUSrcA
RegWriteOp
Funct
ControlUnit
Zero
PCSrc
CLK
CLK
ALUControl2:0
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
MC542 3.68
Processador MIPS Multicycle
Element Parameter Delay (ps)
Register clock-to-Q
tpcq_PC30
Register setup tsetup20
Multiplexer tmux25
ALU tALU200
Memory read tmem250
Register file read
tRFread150
Register file setup
tRFsetup20
Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup
= tpcq_PC + tmux + tmem + tsetup
= [30 + 25 + 250 + 20] ps = 325 ps
MC542 3.69
Processador MIPS Multicycle
• Para um programa que executa 100 bilhões de instruções em um MIPS multicycle,
• CPI = 4.12
• Tc = 325 ps
Execution Time = (# instructions) × CPI × Tc
= (100 × 109)(4.12)(325 × 10-12)
= 133.9 seconds
• Ele é mais lento do que o MIPS single-cycle (95 segundos). Por que?
– Os passos não tem o mesmo tamanho
– Overhead do seqüenciamento de cada passo (tpcq + tsetup= 50 ps)
MC542 3.70
Revisão: Processador MIPS Single Cycle
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542 3.71
Revisão: Processador MIPS Multicycle
ImmExt
CLK
ARD
Instr / DataMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1PC0
1
PC' Instr25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
ZeroCLK
ALU
WD
WE
CLK
Adr
0
1Data
CLK
CLK
A
B00
01
10
11
4
CLK
ENEN
00
01
10
<<2
25:0 (Addr)
31:28
27:0
PCJump
5:0
31:26
Branch
MemWrite
ALUSrcA
RegWriteOp
Funct
ControlUnit
PCSrc
CLK
ALUControl2:0
ALUSrcB1:0IRWrite
IorD
PCWritePCEn
Re
gD
st
Mem
toReg